Nanoinformatics TRIZ Cases

Electrically connected gate segments across an active cut boost nanosheet MBCFET density while suppressing short channel effects.

Separation and gate-cut patterns guide substrate removal to expose source/drain regions and improve through-via contact during back wiring.

Protective dielectric and dummy gate oxide layers preserve the active fin during high-aspect-ratio gate etching and improve electrical stability.

A dummy channel stack and barrier layer align stacked source/drain regions to block substrate leakage and preserve device performance.

Integral silicide via portions connect source and drain from both sides, increasing 3DIC routing density without extra TSV area.

An SOI nanosheet transistor isolates the gate from the substrate, cutting leakage while avoiding extra implant steps and process complexity.

A temporary source/drain stressor tunes GAA FET channels, then is removed after metal gate formation to cut capacitance, leakage, and resistance.

A two-material gate isolation stack separates adjacent gates in FinFET and GAA structures to reduce leakage and parasitic capacitance.

A single self-aligned contact joins top and bottom gate conductors to improve stacked transistor alignment and lower gate resistance.

A merged gate and contact separation pattern improves plug isolation and vertical connectivity while easing alignment in 3D transistor fabrication.

Absorptive metastructures in unpopulated frame-pixel regions cut reflection, improving signal-to-noise ratio and viewing angles in diffractive displays.

A substrate isolation layer and higher-doped APT region under GAA source/drain features reduce junction leakage and latch-up without disrupting current processing.

Using a dummy channel stack and barrier layer, this case aligns stacked source/drain regions to curb substrate leakage without substrate patterning.

Segmented high-k dielectric isolation improves component separation in scaled ICs while limiting capacitance growth and current leakage.

An air gap above the source/drain contact cuts parasitic capacitance in scaled semiconductor layouts while preserving contact reliability.

Segmented insulating structures extend around channel and source/drain regions to improve spacing, block leakage current, and support dense semiconductor integration.

A conformal dipole layer formed by cyclic deposition etch tunes GAA transistor threshold voltage without ultra-thin metal thickness limits.

Different work function film thicknesses in a wraparound multi-gate stack enable multiple threshold voltages while suppressing short channel effects.

A diffusion barrier between doped source/drain regions and SiGe channels suppresses phosphorous migration while keeping contact resistance low.

GAA SRAM layout tuning raises the pull-down to pass-gate β ratio, improving read stability in scaled high-density memory cells.

A two-part gate cut formed before and after gate patterning improves isolation between adjacent fins without difficult deep-etch selectivity.

Segmenting the uppermost GAA MBCFET channel cuts parasitic capacitance while preserving strong gate control and AC performance.

Anisotropic etching and sidewall spacers form recess profiles that improve GAA FET gate control while limiting epitaxial damage.

Sidewall metallization enables frontside and backside wrap-around source/drain contacts, increasing contact area and easing spacing limits in scaled MOSFETs.

Vertical GAA active layers and horizontal capacitors raise memory density without pushing linewidth scaling into harder manufacturing limits.

A metal-doped graphene layer blocks hydrogen diffusion and preserves threshold voltage in oxide transistors as channel lengths shrink.

Sacrificial gate patterning and selective trench etching improve meta-gate height control and reduce variation in 3D transistor fabrication.

Thin dual middle dielectric isolation keeps stacked nanosheet FETs electrically separated, preventing epitaxy shorts without thick-layer defects.

A silicon-rich cap protects high-Ge, high-B SiGe:B PMOS contacts, keeping resistivity ultra-low and stable through 450°C processing.

Selective etching reshapes stacked source/drain layers so the contact plug lands on a higher-doped region, lowering resistance in GAA transistors.

Asymmetric gate-end spacing and protruding source/drain regions reduce gate-channel overlap, lowering parasitic capacitance and improving speed.

Air gaps and porous dielectric spacers cut gate-to-source/drain capacitance while preserving channel resistance in nanosheet transistors.

Layered monocrystalline, polycrystalline, and amorphous source/drain films improve current control and suppress short-channel effects in scaled multi-gate transistors.

Alternating semiconductor and non-semiconductor monolayers boost GAA carrier mobility while tuning work function and limiting dopant diffusion.

Vertically stacked channels and enclosing gate metals shrink logic cell area while preserving MOSFET electrical characteristics.

A channel-last TMD gate-all-around structure reduces material damage, improves gate control, and limits leakage in scaled transistors.

Varying dielectric thickness on the nanosheet and source/drain regions cuts gate leakage and improves scaled IC reliability.

A bridged TMD gate-stack structure enables gate-all-around MBCFET scaling while limiting channel damage and short channel effects.

A split gate contacting an intermediate semiconductor layer suppresses SOI floating body effects while preserving gate control and current density.

A curved inner spacer in a GAA transistor expands source/drain contact to channel layers, boosting drive current and channel control.

Vertically stacked channels and narrow gap-fill regions help scaled MOSFETs preserve operating characteristics and reliability.

A stacked MOSFET with inner spacers and a 2D layer cuts capacitance and improves electron mobility as device dimensions shrink.

Alternating wider NFET and PFET channels across 3D-stacked transistor structures raises density while balancing speed, power, and manufacturability.

Segmented gate insulation uses low- and high-k layers around sheet channels to cut capacitance while preserving heat discharge and current control.

Vertical frontside-backside wiring and via overlap control cut contact capacitance while preserving electrical stability in dense semiconductor layouts.

Low-k inner spacers formed after source-drain epitaxy cut parasitic capacitance while improving channel stress and carrier mobility.

Selective channel-layer counts let one chip tune GAA transistors for high-drive or low-leakage regions while lowering power rail resistance.

A two-angle gate cut isolation profile opens space between nanosheet fins, improving work-function metal and conductive fill coverage.

A PVD-formed first metal and glue layer protect the silicide during CVD via filling, improving source/drain contact reliability.

A template layer and soak or spike anneal control high-k gate dielectric grain size, improving process stability and nano-FET scaling.