Nanosheet MBCFET Gate Layout for Dense Short-Channel Control
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Solution Overview
Problem
Existing multi-gate transistors face challenges in enhancing integration density and suppressing short channel effects while maintaining effective current control.
Innovation Solution
A semiconductor device is designed with a Multi-Bridge Channel Field Effect Transistor (MBCFET) that electrically connects adjacent gate electrodes using portions of the gate electrodes on the upper surface of the active cut, incorporating nanosheets and multiple gate electrodes to enhance integration density and current control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate transistors are used to improve current control and suppress short channel effects, then device performance is improved, but integration density is reduced due to increased gate length requirements
Solution Approach 1:
The gate electrode is divided into multiple segments (first gate electrode, second gate electrode, third gate electrode) that are spatially separated but electrically connected. This segmentation allows each gate segment to independently control a portion of the channel, improving current control capability while maintaining compact layout for high integration density
Solution Approach 2:
The patent transitions from planar gate structures to three-dimensional vertical gate structures. The nanosheets are arranged vertically, and the gate electrodes wrap around them in multiple directions, utilizing the third dimension (vertical direction) to achieve effective multi-gate control without increasing the lateral footprint, thereby maintaining high integration density
2Productivity
If traditional planar transistors are used to maintain high integration density, then device density is improved, but short channel effects cannot be effectively suppressed
Solution Approach 1:
The gate electrodes are nested around the vertical nanosheet channel structures. The first gate electrode surrounds the nanosheets in one direction, while the second and third gate electrodes provide additional control from other directions. This nested configuration achieves multi-gate control with superior short channel effect suppression while maintaining a compact footprint for high integration density
Solution Approach 2:
The invention moves from two-dimensional planar gates to three-dimensional vertical gates that wrap around nanosheet channels. This dimensional transition enables effective electrostatic control of the channel from multiple directions, suppressing short channel effects while keeping the device footprint small for high integration density
3Reliability
If gate length is increased to suppress short channel effects, then short channel effect suppression is improved, but integration density is reduced
Solution Approach 1:
Instead of increasing gate length in the lateral direction, the patent employs vertical nanosheet channels with gate electrodes that wrap around them in three dimensions. This approach achieves effective short channel effect suppression through enhanced electrostatic control from multiple directions without increasing the lateral gate length, thereby maintaining high integration density
Solution Approach 2:
Multiple gate electrodes are nested around the vertical channel, providing comprehensive control. The first gate electrode controls from one direction, while the second and third gate electrodes provide control from additional directions. This nested multi-gate configuration achieves superior short channel effect suppression with compact lateral dimensions for high integration density
Data Source
AI summary
A semiconductor device includes a lower interlayer insulating layer, an insulating pattern extending in a first direction on the lower interlayer insulating layer, a plurality of nanosheets on the insulating pattern and spaced apart in a third direction, an active cut penetrating the lower interlayer insulating layer, the insulating pattern and the plurality of nanosheets, the active cut extending in a second direction and comprising an upper surface extending between opposing first and second sidewalls, and a first gate electrode extending in the second direction on the insulating pattern, wherein the first gate electrode includes a first portion in contact with the first sidewall of the active cut in the second direction, a second portion in contact with the upper surface of the active cut, and a third portion in contact with the second sidewall of the active cut, where the second connects the first portion and the third portion.