TMD Gate-Stack Bridge Structure for GAA MBCFET Scaling

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Solution Overview

Problem

The miniaturization of semiconductor processes poses challenges in applying existing silicon-based processes to transition metal dichalcogenide (TMD) materials, leading to potential damage and difficulty in maintaining the quality of TMD materials in multi-bridge channel field-effect transistors (MBCFETs) with gate-all-around (GAA) structures.

Innovation Solution

A semiconductor device is designed with a first and second gate stack, each comprising channel layers and gate electrodes, connected by a bridge, and surrounded by a gate insulating layer, utilizing TMD materials for the channel layers and TiN for the bridge, with symmetric or asymmetric configurations to enhance gate control and minimize damage during manufacturing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If existing silicon-based processes are applied to TMD materials, then manufacturing process compatibility is improved, but damage to TMD materials occurs and material quality deteriorates

Engineering Contradiction:
Improveprocess compatibilityVSAvoidTMD material quality
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent modifies process parameters specifically for TMD materials, including using lower temperature processes (below 400°C), adjusted etching conditions, and modified deposition parameters to prevent damage while maintaining manufacturing feasibility

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces intermediate protective layers and buffer structures that mediate between the silicon-based process equipment and the sensitive TMD materials, preventing direct damage while allowing process compatibility

Inventive Principle:
Principle #24Intermediary (Mediator)

2Length of moving object

If transistor sizes are decreased for miniaturization, then device scaling is improved, but short channel effects increase and gate control deteriorates

Engineering Contradiction:
Improvetransistor sizeVSAvoidgate control
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent transitions from planar gate structures to three-dimensional gate-all-around structures, wrapping the gate electrode around the channel in multiple dimensions to enhance control over the charge carrier flow despite reduced channel length

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs composite material structures including high-k dielectric materials combined with metal gate electrodes, and multi-layer channel structures with different TMD materials to improve gate control efficiency in scaled devices

Inventive Principle:
Principle #40Composite materials

3Reliability

If gate-all-around structures are implemented to reduce short channel effects, then gate control is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvegate controlVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the gate structure into segmented components including separate gate electrode layers, insulating layers, and channel layers that can be manufactured using modular process steps, reducing overall manufacturing complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent designs the gate-all-around structure to serve multiple functions simultaneously: electrical gating, mechanical support, and stress control, reducing the need for additional separate components and simplifying the overall device architecture

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260068302A1Semiconductor device and method of manufacturing the semiconductor device
Publication Date: 2026.03.05 SAMSUNG ELECTRONICS CO LTD
  • US20260068302A1 patent drawing
  • US20260068302A1 patent drawing
  • US20260068302A1 patent drawing

AI summary

A semiconductor device may include a first gate stack, a second gate stack, and a bridge. The first gate stack may include a first channel layer and a plurality of first gate electrodes provided respectively on an upper portion of the first channel layer and a lower portion of the first channel layer. The second gate stack may include a second channel layer and a plurality of second gate electrodes provided respectively on an upper portion of the second channel layer and a lower portion of the second channel layer. The bridge may connect the first gate stack and the second gate stack to each other.