Nanosheet Transistor Air-Gap Spacers for Lower Parasitic Capacitance
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to reduce parasitic capacitance between source/drain features and gate while maintaining desired K value for devices, particularly in nanosheet transistors, as scaling down processes lead to increased channel resistance and reduced current conductivity.
Innovation Solution
A method involving the formation of air gaps and dielectric spacers in nanosheet transistors, where sacrificial dielectric layers are used to preserve the integrity of semiconductor layers during epitaxial source/drain feature formation, reducing gate-to-source/drain capacitance by forming air gaps and using dielectric spacers with controlled porosity and thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down process is used to increase functional density, then production efficiency and cost are improved, but parasitic capacitance between source/drain features and gate increases
Solution Approach 1:
The patent extracts the harmful dielectric material between source/drain features and replaces it with air gaps. By removing the solid dielectric that causes parasitic capacitance and replacing it with air (which has minimal capacitance), the harmful electrical coupling is eliminated while maintaining the physical structure needed for device operation.
Solution Approach 2:
The patent employs porous or hollow dielectric spacers containing air gaps within the gate structure. These porous regions create air-filled cavities between the gate and source/drain features, reducing the effective dielectric constant in the capacitance-forming region and thereby minimizing parasitic capacitance while preserving gate control.
2Length of moving object
If scaling down process is used to increase functional density, then geometry size is reduced, but channel resistance increases
Solution Approach 1:
The patent uses composite gate structures combining different materials with complementary properties. The gate includes regions with varying dielectric constants and conductive materials optimized for different functions: high-k dielectric for gate control, conductive fills for low resistance, and air gaps for capacitance reduction. This composite approach allows simultaneous optimization of channel resistance and parasitic capacitance.
3Object-generated harmful factors
If dielectric spacers with controlled porosity are used to reduce parasitic capacitance, then gate-to-source/drain capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent forms the porous dielectric spacers with air gaps during earlier fabrication steps before final gate patterning. By pre-forming these capacitance-reducing structures as part of the spacer deposition process, the need for additional complex post-processing steps is eliminated, and the air gaps are already in place to reduce parasitic capacitance during subsequent manufacturing operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate-to-source/drain capacitance by 3-4% and maintains channel resistance, ensuring efficient current flow and device performance in nanosheet transistors.
Implementation Method 1
during epitaxial source/drain feature formation
Implementation Method 2
reducing gate-to-source/drain capacitance by forming air gaps
Implementation Method 3
using dielectric spacers with controlled porosity and thickness
Data Source
AI summary
Various embodiments of the present disclosure provide a method for forming a semiconductor device structure. In one embodiment, the method includes forming a fin over a substrate, wherein the fin comprises first semiconductor layers and second semiconductor layers alternating stacked. The method also includes forming a sacrificial gate structure over the fin, removing portions of the fin not covered by the sacrificial gate structure, replacing the second semiconductor layers with a sacrificial dielectric material, recessing edge portions of the sacrificial dielectric material to form cavities between the first semiconductor layers, forming a dielectric spacer in the cavities by depositing a conformal layer of a dielectric liner layer on exposed surfaces of each cavity, forming source/drain features on opposite sides of the sacrificial gate structure, and replacing the sacrificial gate structure and the sacrificial dielectric material with a gate structure wrapping around the first semiconductor layers.