Low-k Inner Spacers for Epitaxial Source-Drain Stress Control
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Solution Overview
Problem
The fabrication of high-density semiconductor devices, particularly gate-all-around (GAA) and forksheet transistors, is complicated by the use of high-k dielectric spacers that increase parasitic capacitance and result in a weak stress profile and lower carrier mobility due to epitaxial growth of source or drain regions from short ends of nanoribbons.
Innovation Solution
Formation of low-k dielectric spacers between the gate structure and source or drain regions, with the source or drain regions grown before spacer formation, allowing for a larger continuous surface and improved stress profile, using materials like silicon dioxide for the spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If high-k dielectric spacers are used, then device spacing is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent applies different dielectric materials with different k-values to different spatial locations: high-k dielectric material is used in the gate dielectric layer close to the channel for high field control, while low-k dielectric material is used in the inner spacer regions away from the channel for low parasitic capacitance. This local differentiation resolves the contradiction by optimizing each region's electrical properties for its specific function.
2Ease of manufacture
If source or drain regions are grown from short ends of nanoribbons, then fabrication is simplified, but stress profile becomes weak and carrier mobility decreases
Solution Approach 1:
The patent performs preliminary actions by forming the low-k inner spacers before growing the source and drain regions. This allows the spacers to be in place during epitaxial growth, guiding the formation of extended source/drain regions that grow along the nanoribbon length rather than from short ends. This preliminary spacer formation enables better stress transfer to the channel while maintaining fabrication feasibility.
3Object-generated harmful factors
If low-k dielectric spacers are formed, then parasitic capacitance is reduced, but fabrication complexity increases
Solution Approach 1:
The patent merges the formation of low-k inner spacers with the existing spacer formation process used in gate-all-around transistor fabrication. The low-k dielectric material is deposited conformally on the nanoribbon surfaces along with the high-k dielectric, and both are etched back together to form the inner spacers. This merging approach reduces fabrication complexity by integrating the low-k spacer formation into existing process steps rather than adding entirely new process modules.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances transistor performance by increasing stress on the channel bodies and improving carrier mobility, while reducing parasitic capacitance.
Implementation Method 1
high-k dielectric spacers that increase parasitic capacitance
Implementation Method 2
epitaxial growth of source or drain regions from short ends of nanoribbons
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3A~3B
AI summary
Techniques are provided herein to form an integrated circuit having semiconductor devices with low-k inner dielectric spacers between semiconductor bodies (e.g., nanoribbons, nanowires, or nanosheets). The dielectric spacers may include any suitable low-k dielectric material. Additionally, the inner dielectric spacers may be formed after the formation of source or drain regions, which improves the stress profile of the source or drain regions against the semiconductor bodies. In one such example, semiconductor bodies extend in a first direction between source or drain regions and a gate structure extends in a second direction over the semiconductor bodies between the source or drain regions. Inner spacers separate the gate structure from the source or drain regions along the first direction. The inner spacers may include a low-k dielectric material, such as silicon dioxide. In some examples, the inner spacers extend outwards beyond the ends of the semiconductor bodies along the first direction.