GAA Transistor Threshold Tuning With Conformal Dipole Layers
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Solution Overview
Problem
The challenge of achieving multiple threshold voltages in field effect transistors (FETs) on the same substrate is constrained by the thickness limitations of work function metal layers, particularly in gate-all-around (GAA) FETs, which become increasingly difficult with scaling down, and depositing precise thicknesses becomes challenging.
Innovation Solution
Incorporating a dipole layer into the gate dielectric layer using a cyclic deposition etch (CDE) process in an atomic layer deposition (ALD) chamber to tune the threshold voltage, combined with work-function tuning layers, ensures uniform dopant distribution and minimal variation in threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If work function metal layer thickness is varied to achieve multiple threshold voltages, then threshold voltage adjustment is possible, but manufacturing precision deteriorates due to thickness limitations and scaling challenges
Solution Approach 1:
The patent introduces a dipole layer as an intermediary component between the gate electrode and channel, consisting of dipole metal elements (such as zinc, cadmium, or mercury) arranged in a specific configuration. This dipole layer mediates the electric field interaction, enabling threshold voltage tuning without requiring precise control of work function metal layer thickness. The dipole moment of the layer provides the necessary electrical characteristic adjustment while avoiding the manufacturing precision issues of thin metal layer deposition.
2Length of moving object
If work function metal layer thickness is reduced for scaling, then device size decreases, but manufacturing precision worsens as depositing precise thicknesses becomes increasingly challenging
Solution Approach 1:
The patent changes the parameter used for threshold voltage control from physical thickness of metal layers to the dipole moment characteristics of the dipole layer. By adjusting the composition, arrangement, or density of dipole metal elements rather than controlling thin film thickness, the method enables scaling to smaller device dimensions while avoiding the exponentially increasing difficulty of depositing ultra-thin metal layers with precise thickness control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method allows for precise adjustment of threshold voltages with minimal variation, enabling the fabrication of transistors with multiple threshold voltages in a CMOS device by ensuring uniform distribution of dipole metal elements in the gate dielectric layer.
Implementation Method 1
The dipole metal elements of the dipole layer are diffused to an interface between the gate dielectric layer and the interfacial layer
Data Source
AI summary
A method for tuning a threshold voltage of a transistor is disclosed. A channel layer is formed over a substrate. An interfacial layer is formed over and surrounds the channel layer. A gate dielectric layer is formed over and surrounds the interfacial layer. A dipole layer is formed over and wraps around the gate dielectric layer by performing a cyclic deposition etch process, and the dipole layer includes dipole metal elements and has a substantially uniform thickness. A thermal drive-in process is performed to drive the dipole metal elements in the dipole layer into the gate dielectric layer to form an interfacial dipole surface, and then the dipole layer is removed.