Dummy Gate Oxide Stack for High-Aspect-Ratio Fin Gate Etching
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Solution Overview
Problem
High aspect ratio gate patterning in semiconductor fabrication faces challenges in maintaining the desired aspect ratio and preventing erosion of the active part of the semiconductor structure during gate etch processes, which affects electrical performance.
Innovation Solution
A method involving the formation of a semiconductor structure with a dielectric layer and dummy gate oxide that ensures etch selectivity and protects the active part from erosion, using materials like SiN, SiCN, SiOCN, and SiOBCN for the dielectric layer and SiO2 for the dummy gate oxide, along with a liner material to facilitate uniformity and robust electrical stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gate patterning is used for high aspect ratio structures, then the gate structures can be formed, but erosion of the active part occurs during gate etch processes affecting electrical performance
Solution Approach 1:
The method performs preliminary actions by forming a dielectric layer on the active part and depositing dummy gate oxide before the gate etch process. This preparatory structure is designed to be removed selectively after serving its protective function, preventing erosion of the active part during high aspect ratio gate patterning
Solution Approach 2:
The dielectric layer and dummy gate oxide serve as intermediary protective structures between the etch process and the active part. These intermediary layers are selectively removed after protecting the active part during gate etching, thereby preventing harmful erosion while maintaining manufacturing precision
2Device complexity
If the dielectric layer is made thinner to reduce complexity, then the structure is simpler, but etch selectivity and protection of the active part are compromised
Solution Approach 1:
The method employs composite material structures with specific dielectric layers and dummy gate oxide compositions that provide enhanced etch selectivity. The composite structure of different dielectric materials with distinct etch rates enables reliable protection of the active part while maintaining a manageable layer complexity
3Reliability
If the dummy gate oxide is made thicker to improve protection, then etch selectivity is improved, but the structure becomes more complex and harder to process
Solution Approach 1:
The method optimizes the thickness parameter of the dummy gate oxide within a specific range to achieve the desired balance between protection reliability and processability. By carefully controlling the thickness parameter, the method ensures sufficient etch selectivity and active part protection while avoiding excessive structural complexity that would hinder subsequent processing steps
Data Source
Figure 1a~1b
Figure 1c~1d
Figure 1e~1f
AI summary
The present invention provides a method for forming a semiconductor structure (100), the method comprising: forming a fin (103) comprising a layer stack (110) on a substrate (102), the layer stack (110) comprising: a first sub-stack (120) comprising: at least one channel layer (122) at least one sacrificial layer (124) a dielectric layer (132) on top of the first sub-stack (120) depositing a dummy gate oxide (142) straddling the fin (103), the dummy gate oxide (142) extending over the dielectric layer (132) of the fin (103), forming a dummy gate (150) on top of the dummy gate oxide (142), the dummy gate (150) straddling the fin (103).