Multilayer Gate Insulation for 3D Transistor Capacitance Control
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Solution Overview
Problem
As semiconductor devices scale, there is a need to improve performance and reliability by reducing capacitance, ensuring heat discharge, and maintaining electrical stability while effectively controlling current, particularly in multi-gate transistors with three-dimensional channels.
Innovation Solution
A semiconductor device design featuring a substrate with active patterns and gate electrodes, incorporating insulating layer structures along the edges of sheet patterns and insertion insulating layers to enhance electrical control and stability, utilizing materials like silicon nitride and high dielectric constant materials to reduce capacitance and improve current control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pitch size is reduced to increase device density, then device density is improved, but capacitance between contacts increases and heat discharge becomes difficult
Solution Approach 1:
The insulating layer is divided into multiple sub-layers (first insulating layer, second insulating layer, third insulating layer) with different dielectric properties. The first insulating layer has lower dielectric constant to reduce capacitance, while the second and third insulating layers have higher dielectric constant to improve heat discharge and electrical stability, creating a segmented approach to simultaneously address multiple performance requirements
Solution Approach 2:
Different regions of the insulating layer structure are assigned different dielectric characteristics. The first insulating layer (closer to the contact) uses material with lower dielectric constant to minimize capacitance, while the second and third insulating layers (deeper regions) use materials with higher dielectric constant to enhance heat discharge capability and electrical stability, optimizing each region for its specific function
2Reliability
If gate length is increased to improve current control capability, then current control capability is improved, but device scaling becomes difficult
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional multi-layer insulating structure around the gate electrode. By adding the first, second, and third insulating layers in different spatial dimensions surrounding the gate, the effective gate control volume is increased without increasing the gate length in the planar direction, thereby maintaining scalability while improving current control capability
Solution Approach 2:
The insulating layer structure uses a composite of multiple dielectric materials with different properties. The first insulating layer uses material with lower dielectric constant (e.g., SiO2) to reduce capacitance, while the second and third insulating layers use materials with higher dielectric constant (e.g., Si3N4, SiON) to improve heat discharge and electrical stability, creating a composite structure that optimizes overall device performance
Data Source
AI summary
Provided is a semiconductor device including a substrate, a first active pattern on the substrate, including a first lower pattern and a plurality of first sheet patterns spaced apart from the first lower pattern, a gate electrode on the substrate, and on the plurality of first sheet patterns, an interfacial layer between the plurality of first sheet patterns and the gate electrode and along the outer edge of each of the plurality of first sheet patterns, and a first insulating layer structure between the interfacial layer and the gate electrode and, wherein the first insulating layer structure includes a first insulating layer along on the interfacial layer, a first insertion insulating layer along on the first insulating layer, and a second insulating layer along on the first insertion insulating layer.