Dummy Channel Stack Layout for Low-Leakage Stacked Semiconductors
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Solution Overview
Problem
The formation of stacked semiconductor devices with complex structures and high-aspect ratios leads to challenges such as current leakage from the source/drain regions into the substrate, affecting device performance.
Innovation Solution
The use of a dummy channel stack and a barrier layer to prevent or reduce current leakage by aligning source/drain regions and ensuring coplanarity, thereby avoiding substrate patterning and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If substrate patterning is performed to form source/drain regions in stacked semiconductor devices, then device density and integration are improved, but current leakage from source/drain regions into the substrate increases
Solution Approach 1:
A dummy channel stack is introduced as an intermediary structure between the substrate and the actual channel stack. This dummy structure prevents direct patterning of the substrate, thereby eliminating current leakage paths while still allowing source/drain regions to be formed at the required positions. The dummy channel stack acts as a placeholder that maintains structural integrity without creating harmful electrical connections.
Solution Approach 2:
The channel stack is divided into a functional channel stack and a dummy channel stack. The dummy portion is specifically designed to prevent substrate patterning and current leakage, while the functional portion maintains device performance. This segmentation allows the system to achieve both high device density and low current leakage by separating the structural support function from the active device function.
2Reliability
If source/drain regions are formed with different dimensions to facilitate contact structure formation, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The dummy channel stack is formed in advance during the channel stack formation process, before source/drain region patterning. This preliminary action establishes the correct geometric relationships and coplanarity between different source/drain regions, simplifying subsequent manufacturing steps. By pre-positioning the dummy structure, the need for complex alignment and patterning adjustments is eliminated.
Solution Approach 2:
The solution addresses dimensional variations in source/drain regions by utilizing the vertical dimension through the dummy channel stack. Instead of managing horizontal dimension variations through complex patterning, the dummy structure provides vertical reference planes that ensure coplanarity. This dimensional approach simplifies the manufacturing process while maintaining different source/drain dimensions for optimal device performance.
Data Source
AI summary
Provided is a stacked semiconductor device which includes: a substrate; a 1st source/drain region on the substrate; and a 2nd source/drain region vertically above the 1st source/drain region, the 2nd source/drain region vertically overlapping a 1st portion, among the 1st portion and a 2nd portion, of the 1st source/drain region, wherein a 1st portion of a top surface of the substrate vertically below the 1st portion of the 1st source/drain region and a 2nd portion of the top surface of the substrate vertically below the 2nd portion of the 1st source/drain region are coplanar or aligned.