SiGe Source/Drain Epitaxy With Diffusion Barrier for Low Contact Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor manufacturing lies in reducing contact resistance and providing appropriate stress to the channel region of FinFETs and GAA FETs, particularly with the use of Ge or SiGe as the channel region, where phosphorous doping leads to diffusion issues affecting device performance.
Innovation Solution
The implementation of epitaxial semiconductor layers with a diffusion barrier layer to suppress impurity diffusion, specifically using silicon-based or silicon germanium-based materials with controlled diffusion coefficients to minimize phosphorous migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phosphorous doping is used to reduce contact resistance in Ge or SiGe channel regions, then contact resistance is reduced, but phosphorous diffusion occurs which degrades device performance
Solution Approach 1:
A diffusion barrier layer is introduced as an intermediary between the phosphorous-doped source/drain region and the Ge or SiGe channel region. This barrier layer, composed of materials such as silicon nitride, tantalum nitride, or tungsten silicide, mediates the interaction by blocking phosphorous diffusion while allowing the doped region to maintain low contact resistance with the channel.
Solution Approach 2:
The source/drain structure is segmented into multiple functional layers: a phosphorous-doped region for contact resistance reduction, a diffusion barrier layer to prevent phosphorous migration, and the Ge or SiGe channel region. This segmentation allows each layer to perform its specific function independently, resolving the contradiction between reducing contact resistance and preventing diffusion.
2Reliability
If higher phosphorous concentration is used to reduce contact resistance, then contact resistance decreases, but diffusion of phosphorous into the channel region increases
Solution Approach 1:
The diffusion barrier layer serves as a mediator that decouples the relationship between phosphorous concentration and diffusion. High phosphorous concentration can be used in the source/drain region to reduce contact resistance without increasing diffusion into the channel, because the barrier layer blocks the diffusion path regardless of the phosphorous concentration in the adjacent doped region.
Solution Approach 2:
The invention changes the material parameter of the barrier layer to have extremely low phosphorous diffusion coefficients. By selecting materials such as silicon nitride or tungsten silicide with appropriate thickness (5-50 nm), the system achieves high phosphorous concentration in the source/drain region while maintaining precise control over phosphorous distribution in the channel region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contact resistance and maintains device performance by preventing phosphorous diffusion, enhancing electron mobility and reliability of FinFETs and GAA FETs.
Implementation Method 1
A source/drain structure is formed in a fin structure. A diffusion barrier layer is formed on a top surface and side surfaces of the source/drain structure. An epitaxial semiconductor layer is formed on the diffusion barrier layer.
Implementation Method 2
The challenge in semiconductor manufacturing lies in reducing contact resistance and providing appropriate stress to the channel region of FinFETs and GAA FETs, particularly with the use of Ge or SiGe as the channel region, where phosphorous doping leads to diffusion issues affecting device performance.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a gate structure is formed over a fin structure. A source/drain region of the fin structure is recessed. A first semiconductor layer is formed over the recessed source/drain region. A second semiconductor layer is formed over the first semiconductor layer. The fin structure is made of SixGe1-x, where 0≤x≤0.3, the first semiconductor layer is made of SiyGe1-y, where 0.45≤y≤1.0, and the second semiconductor layer is made of SizGe1-z, where 0≤z≤0.3.