Source/Drain Layer Shaping for Lower GAA Contact Resistance
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Solution Overview
Problem
The increasing complexity of Integrated Circuit (IC) manufacturing, particularly in the development of Gate-All-Around (GAA) transistors, poses challenges in reducing contact resistance between the source/drain contact plug and the source/drain region, which affects the performance and efficiency of these advanced transistor structures.
Innovation Solution
The formation of source/drain regions in GAA transistors involves etching back a layer with a lower dopant concentration to reduce the size of its upper portions, creating more space for a higher-dopant-concentration layer, ensuring the contact plug lands on this layer and is spaced apart from the lower-dopant-concentration layer, thereby reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source/drain contact plug is formed to contact the source/drain region, then electrical connection is established, but contact resistance increases due to the small geometry sizes and complex structures in GAA transistors
Solution Approach 1:
The source/drain region is segmented into multiple layers with different dopant concentrations. The contact plug is configured to contact specifically the higher-dopant-concentration layer while being spaced from the lower-dopant-concentration layer, creating distinct functional zones that optimize electrical connection while managing the complex GAA transistor structure.
Solution Approach 2:
Different regions of the source/drain structure are assigned different dopant concentrations to optimize local electrical properties. The higher-dopant-concentration layer provides low-resistance contact paths where needed, while the lower-dopant-concentration layer maintains appropriate spacing and structural integrity, addressing contact resistance issues without requiring uniform structural modification throughout the entire device.
2Productivity
If geometry sizes are reduced to increase functional density, then production efficiency improves and costs decrease, but contact resistance between contact plug and source/drain region increases
Solution Approach 1:
The dopant concentration parameter is varied across different layers of the source/drain region. By creating a vertical gradient in dopant concentration rather than using uniform doping, the structure maintains low contact resistance despite reduced lateral dimensions, enabling continued scaling while preserving electrical performance.
Solution Approach 2:
The solution moves from lateral dimension optimization to vertical dimension exploitation. By stacking multiple source/drain layers with different dopant concentrations in the vertical direction, the invention compensates for reduced lateral contact area, maintaining adequate contact resistance performance even as device footprint is minimized for higher density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the reliability and efficiency of contact resistance reduction between the source/drain contact plug and the source/drain region, improving the overall performance of GAA transistors.
Implementation Method 1
A layer of the source/drain region having a relatively lower dopant concentration is etched back, so that the upper portions of the layer have smaller sizes than respective lower portions
Data Source
AI summary
A method includes forming a plurality of semiconductor nanostructures, wherein upper ones of the plurality of semiconductor nanostructures overlap respective lower ones of the plurality of semiconductor nanostructures. A plurality of semiconductor layers are formed, each from one of the plurality of semiconductor nanostructures. The plurality of semiconductor layers are shaped through an etching process. A first semiconductor layer of the plurality of semiconductor layers is etched more than a second semiconductor layer of the plurality of semiconductor layers, wherein the first semiconductor layer is higher than the second semiconductor layer. After the plurality of semiconductor layers are shaped, an additional semiconductor layer is formed to electrically connect to the plurality of semiconductor layers.