SOI Nanosheet Gate Structure for Substrate Leakage Isolation
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Solution Overview
Problem
Existing semiconductor structures, such as nanosheet transistors, face challenges with substrate leakage due to the need for extra implant processes to introduce dopants into the gate structure, which complicates manufacturing and reduces efficiency.
Innovation Solution
A semiconductor device with a fin structure and epitaxial source/drain structure is developed on a semiconductor-on-insulator substrate, where the gate structure is formed without direct contact with the substrate, using epitaxial growth and thermal processes to create sacrificial layers that are later replaced, eliminating the need for substrate contact and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extra implant processes are used to implant dopants into the bottom of the gate structure, then substrate leakage is reduced, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent applies preliminary action by forming the insulator layer between the gate structure and substrate before completing the gate structure formation. This pre-positioned insulator layer proactively prevents substrate leakage from the outset, eliminating the need for subsequent implant processes to address leakage issues.
Solution Approach 2:
The patent extracts the problematic direct contact between the gate structure and substrate by removing the substrate surface layer and replacing it with an insulator layer. This separation removes the source of substrate leakage, making additional implant processes unnecessary.
2Ease of manufacture
If the gate structure directly contacts the substrate, then manufacturing is simpler, but substrate leakage occurs
Solution Approach 1:
The patent introduces an insulator layer as an intermediary between the gate structure and substrate. This intermediate layer mediates the relationship by providing electrical isolation, preventing substrate leakage while maintaining structural integrity and simplifying the overall manufacturing approach.
Solution Approach 2:
The patent segments the gate structure formation process into distinct stages: first forming the insulator layer on the substrate, then forming the gate structure above it. This segmentation allows each component to be optimized independently, achieving both manufacturing simplicity and leakage prevention.
3Productivity
If scaling down is pursued to increase production efficiency, then area is reduced, but processing complexity increases
Solution Approach 1:
The patent addresses scaling challenges by transitioning to a gate-all-around three-dimensional structure with the insulator layer positioned in the vertical dimension between gate and substrate. This dimensional approach enables continued scaling while maintaining manufacturing efficiency through standardized layer formation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively eliminates substrate leakage by isolating the gate structure from the substrate, simplifying manufacturing and improving the efficiency of semiconductor devices like FinFETs.
Implementation Method 1
epitaxially growing a semiconductor capping layer on the top semiconductor layer. The semiconductor capping layer contains the first semiconductor atoms and second semiconductor atoms
Implementation Method 2
performing a thermal process to drive the second semiconductor atoms of the semiconductor capping layer into the top semiconductor layer
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate, a fin structure and an epitaxial source/drain structure. The substrate includes a substrate layer and an insulator layer on the substrate layer. The fin structure is formed over the substrate, wherein the fin structure includes a gate structure and channel layers wrapped by the gate structure. The epitaxial source/drain structure is connected to the channel layers, wherein a bottom portion of the epitaxial source/drain structure is in contact with the insulator layer of the substrate.