Stacked Channel Gate Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high density and efficient operation due to limitations in gate design, leading to increased parasitic capacitance and reduced operating speed.
Innovation Solution
A semiconductor device with vertically stacked channel layers and a gate electrode configuration where the source/drain layers protrude beyond the gate electrode ends, reducing parasitic capacitance and optimizing the gate-channel overlap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the source/drain layer is positioned to contact the channel layers, then electrical connection is achieved, but parasitic capacitance increases due to gate-channel overlap
Solution Approach 1:
The gate electrode is designed with asymmetric extension lengths on either side, where the first extension length beyond the channel layer is different from the second extension length. This asymmetric configuration optimizes the balance between achieving necessary electrical connections and minimizing parasitic capacitance by reducing unnecessary overlap areas while maintaining functional contact regions.
Solution Approach 2:
The gate electrode exhibits different local properties at its ends: one end extends further to ensure proper electrical connection and control, while the other end extends less to minimize parasitic capacitance. This local differentiation allows each region of the gate to serve its specific function optimally, with the source/drain layer positioned to contact channel layers at the region with appropriate overlap.
2Reliability
If the gate electrode extends beyond the channel layer, then gate control is improved, but device complexity increases
Solution Approach 1:
The gate electrode extends partially beyond the channel layer on each side, with the extension lengths carefully controlled to be different from each other. This partial extension provides sufficient gate control for proper device operation without the excessive extension that would create unnecessary complexity in the device structure and fabrication processes.
Data Source
AI summary
A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers.