Stacked MOSFET Structure With 2D Layer for Low-Capacitance Scaling
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operation characteristics, necessitating improvements in electrical and reliability characteristics.
Innovation Solution
The semiconductor device incorporates a specific structure with overlapping semiconductor patterns, a gate electrode, inner spacers, two-dimensional layers, and source/drain patterns, featuring inner and upper spacers with flat side surfaces and uniform germanium concentration in the source/drain patterns to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to reduce pattern size and design rule, then device density increases, but operation characteristics deteriorate
Solution Approach 1:
The patent introduces a three-dimensional stacked structure with multiple semiconductor patterns arranged vertically, transitioning from planar two-dimensional device layout to three-dimensional architecture. This dimensional change allows continued scaling benefits while maintaining electrical performance through increased vertical channel control and reduced short-channel effects
Solution Approach 2:
The patent implements nested structures where inner spacers are positioned within outer spacers, and multiple semiconductor patterns are stacked within a confined vertical space. This nesting approach maximizes device density while maintaining proper electrical isolation and control, resolving the contradiction between miniaturization and operational reliability
2Reliability
If inner spacer area is reduced to minimize capacitance, then electron mobility improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs asymmetric spacer design where inner spacers have different dimensions compared to outer spacers, with inner spacers specifically optimized to have smaller areas. This asymmetric configuration enables selective capacitance reduction in critical regions while maintaining structural integrity and simplifying manufacturing by using different spacer sizes rather than requiring precise control of uniformly small spacers
3Reliability
If germanium concentration is uniform in source/drain patterns, then electron mobility improves, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes parameter changes by introducing uniform germanium concentration as a controlled material parameter in the source/drain patterns. This parameter change transforms the electrical characteristics to improve electron mobility, and the uniformity requirement is managed through standardized deposition processes rather than complex spatially-varying concentration profiles
4Reliability
If side surfaces of semiconductor patterns and inner spacer are made coplanar, then capacitance reduces, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by forming the inner spacers with predetermined dimensions and positions before subsequent semiconductor pattern formation. This sequence ensures that the side surfaces naturally align in the same plane, achieving the coplanar configuration that reduces capacitance while avoiding the need for high-precision post-alignment operations
Data Source
AI summary
An example semiconductor device may include a first semiconductor pattern and a second semiconductor pattern overlapping each other, a gate electrode including an electrode portion between the first semiconductor pattern and the second semiconductor pattern, an inner spacer contacting a top surface of the first semiconductor pattern and a bottom surface of the second semiconductor pattern, a two-dimensional layer contacting the first semiconductor pattern, the second semiconductor pattern, and the inner spacer, and a source/drain pattern on the two-dimensional layer.