Deep Trench Gate Cut Profile for Nanosheet Gate Fill Coverage
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Solution Overview
Problem
In advanced semiconductor devices, the proximity of the backfilled layer to adjacent fins in nanosheet FETs results in insufficient space for deposition of a complete functional gate structure, making it difficult to form gate cut openings and leading to issues like void formation during the deposition of work function materials and metal conductive fill materials.
Innovation Solution
A gate cut isolation region with a profile discontinuity is created by forming a top portion and a bottom portion with different taper angles, allowing for better space between nanosheet fins and improved coverage of work function metals, achieved by using dummy gate materials with varying etch rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate cut isolation region is formed with a single taper angle, then the fabrication process is simple, but there is insufficient space for deposition of functional gate structure between adjacent fins
Solution Approach 1:
The gate cut isolation region is divided into two distinct portions: a first portion with a first taper angle and a second portion with a second taper angle. This segmentation allows each portion to serve different functional purposes - the first portion provides structural support while the second portion creates adequate space for functional gate structure deposition between adjacent fins, thereby resolving the contradiction between fabrication simplicity and deposition space.
Solution Approach 2:
Different taper angles are applied to different portions of the gate cut isolation region based on local requirements. The first portion uses a first taper angle optimized for structural integrity, while the second portion uses a second taper angle optimized for creating deposition space. This local differentiation resolves the contradiction by tailoring the geometry to specific functional needs rather than applying a uniform approach.
2Reliability
If dummy gate materials with varying etch rates are used, then coverage of work function metals is improved, but the fabrication process becomes more complex
Solution Approach 1:
The etch rate parameter is varied by using different dummy gate materials (first dummy gate material with first etch rate, second dummy gate material with second etch rate). This parameter change enables selective removal of dummy gate materials to create the desired profile discontinuity and improve coverage of work function metals, while the materials are selected from standard semiconductor materials to minimize process complexity.
Solution Approach 2:
Dummy gate materials serve as intermediary structures that are temporarily introduced to enable the formation of the desired gate cut isolation region profile. These intermediaries are selectively removed through etching processes with different etch rates, allowing precise control over the final geometry without requiring direct formation of the complex structure, thus improving metal coverage while managing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the deposition of work function metals and metal conductive fill materials, improving the coverage and reliability of the gate structure, thereby increasing device performance and reliability.
Implementation Method 1
an etch rate of the first dummy gate material is higher than an etch rate of the second dummy gate material
Data Source
AI summary
A semiconductor structure includes a gate cut isolation region composed of a top portion and a bottom portion. The top portion of the gate cut isolation region being at a first taper angle and the second portion being at a second taper angle different from the first taper angle. A change from the first taper angle to the second taper angle occurs at an intersection between the top portion of the gate cut isolation region and the bottom portion of the gate cut isolation region. The semiconductor structure further includes a plurality of semiconductor channel layers adjacent to the gate cut isolation region, the plurality of semiconductor channel layers being surrounded by a metal gate stack. A top surface of an uppermost semiconductor channel layer being coplanar with the intersection between the top portion and the bottom portion of the gate cut isolation region.