3D Stacked Transistor Gate Structure for Higher Logic Density
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in integration density and electrical characteristics.
Innovation Solution
A three-dimensional semiconductor device design featuring vertically stacked transistors with distinct source/drain regions and channel structures, along with a gate electrode that encloses semiconductor layers, allowing for increased integration density and improved electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOS-FETs are scaled down to meet demand for small pattern size and reduced design rule, then integration density increases, but operational properties deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertically stacked transistors. Multiple channel structures are stacked vertically along the third dimension, allowing increased integration density without further scaling of the lateral dimensions. This dimensional change enables more transistors to be packed in the same footprint area while maintaining larger effective channel dimensions for better operational properties.
Solution Approach 2:
The gate electrode structure wraps around and encloses the channel structures in a nested configuration. The gate electrode forms a surrounding structure that contains multiple semiconductor layers and channel regions, with the gate enclosing the channels from multiple sides. This nested arrangement improves gate control over the channel while maintaining compact vertical stacking.
2Area of stationary object
If vertically stacked transistor structure is implemented, then integration density increases and area is reduced, but device complexity increases
Solution Approach 1:
The vertically stacked transistor structure is divided into multiple discrete semiconductor layers, each forming a separate channel. The gate electrode is segmented into multiple gate structures that individually control each channel layer. This segmentation allows independent optimization of each layer's electrical characteristics while maintaining the compact vertical stack, reducing the overall logic cell area.
Solution Approach 2:
The vertically stacked gate electrode structure serves multiple functions simultaneously: it provides electrical control over multiple channel layers, acts as a mechanical support framework for the stacked configuration, and defines the active regions for multiple transistors sharing common source/drain structures. This multi-functionality reduces the need for additional separate components, offsetting the increased structural complexity.
Data Source
AI summary
Disclosed are a three-dimensional semiconductor device and a method of fabricating the same. The semiconductor device includes: a first active region on a substrate, the first active region including a pair of lower source/drain regions and a lower channel structure; a second active region on the first active region, the second active region including a pair of upper source/drain regions and an upper channel structure; and a gate electrode on the lower and upper channel structures. The gate electrode includes: first and second metal structures, which are respectively provided adjacent bottom and top surfaces of semiconductor layers of the lower and upper channel structures.