SiGe:B PMOS Contact Stack With Silicon Cap for Thermal Stability
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Solution Overview
Problem
The challenge in integrated circuit fabrication is achieving ultra-low PMOS contact resistivity and thermal stability in transistors, particularly in multi-gate and nanowire structures, due to the difficulty in balancing germanium and boron doping, etch resistance, and thermal instability of titanium silicide contacts.
Innovation Solution
A low temperature, high germanium, high boron SiGe:B pEPI with a silicon rich capping layer is used to form epitaxial source/drain structures, which are protected by a second pEPI region and a silicon capping layer to minimize contact resistivity and ensure thermal stability, even under high temperature processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high germanium and high boron doping is used to reduce contact resistivity, then contact resistivity decreases, but thermal stability deteriorates due to titanium silicide contact instability at high temperatures
Solution Approach 1:
A silicon-rich capping layer is introduced as an intermediary protective layer between the titanium silicide contact and the high germanium/high boron SiGe:B epitaxial region. This capping layer acts as a barrier that prevents titanium diffusion into the SiGe:B region during high-temperature processing, thereby maintaining both low contact resistivity and thermal stability. The capping layer is strategically positioned to mediate the interaction between the contact metal and the doped semiconductor region.
Solution Approach 2:
The contact structure employs a composite material system consisting of multiple layers with distinct compositions and functions: a silicon-rich capping layer, a high germanium/high boron SiGe:B epitaxial layer, and titanium silicide contact. Each layer contributes specific properties - the silicon-rich capping provides thermal stability, the SiGe:B layer provides low resistivity, and the titanium silicide provides good adhesion and conductivity. This composite structure resolves the contradiction by combining materials with complementary properties.
2Manufacturing precision
If low temperature epitaxial growth is used to maintain high germanium content, then germanium incorporation improves, but etch resistance deteriorates
Solution Approach 1:
The patent utilizes parameter changes in the epitaxial growth process, specifically controlling temperature, pressure, and gas flow conditions to optimize germanium incorporation at low temperatures. By adjusting these parameters, the process achieves high germanium content (exceeding 50 atomic percent) while maintaining adequate etch resistance through controlled crystal structure formation and doping during the low-temperature growth.
3Productivity
If feature dimensions are scaled down to increase device density, then device capacity increases, but short channel control deteriorates
Solution Approach 1:
The patent transitions from planar transistor geometry to three-dimensional FinFET structures, where the channel is formed as a vertical fin with the gate wrapping around it. This dimensional change from 2D to 3D architecture provides superior electrostatic control over the channel, enabling effective short channel control even at scaled dimensions. The vertical fin structure increases the effective channel width while maintaining excellent gate control, thereby achieving high device density without sacrificing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in PMOS contact resistivity of less than 1×10−9 Ohm cm² with thermal stability up to 450°C, compatible with high volume manufacturing and enhancing transistor performance.
Implementation Method 1
a silicon rich capping layer for ultra-low PMOS contact resistivity and thermal stability
Implementation Method 2
low temperature, high germanium, high boron SiGe:B pEPI
Data Source
AI summary
Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise i) a first PMOS epitaxial (pEPI) region of germanium and boron, ii) a second pEPI region of silicon, germanium and boron on the first pEPI region at a contact location, iii) a capping layer comprising silicon over the second pEPI region. A conductive contact material comprising titanium is on the capping layer.