Multi-Gate Sheet Transistor Source/Drain Structure for Short-Channel Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in scaling density and improving current control capabilities while effectively suppressing the short channel effect, which affects channel area potential by drain voltage.
Innovation Solution
The semiconductor device incorporates a multi-gate structure with a monocrystalline, polycrystalline, and amorphous semiconductor material films in the source/drain pattern, enhancing current control and reliability through a specific arrangement of active and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are used to increase device density, then scaling capability is improved, but manufacturing complexity increases due to the need for precise multi-layer alignment
Solution Approach 1:
The source/drain structure is segmented into multiple semiconductor material films with different crystalline structures (amorphous, polycrystalline, and monocrystalline layers). This segmentation allows each layer to serve a specific function: the amorphous layer provides conformal coverage, the polycrystalline layer provides structural stability, and the monocrystalline layer provides high-quality carrier transport. This resolves the contradiction by breaking down the complex multi-gate structure into manageable functional segments that can be manufactured with standard processes.
Solution Approach 2:
The patent employs a composite material approach by combining multiple semiconductor material films with different crystalline structures in a single source/drain region. This composite structure leverages the advantages of each material type: amorphous materials for conformal deposition, polycrystalline materials for structural robustness, and monocrystalline materials for superior electrical performance. This composite approach enables high device density while maintaining manufacturability through standard semiconductor processing techniques.
2Reliability
If gate length is increased to improve current control, then current control capability is improved, but device scaling is limited
Solution Approach 1:
The patent transitions from conventional planar gate structures to multi-gate structures that wrap around the channel in three dimensions. This dimensional change allows the gate to control the channel from multiple directions (top, bottom, and sides), significantly improving current control capability without increasing the planar gate length. The multi-gate configuration enables effective channel control while maintaining scaled-down device dimensions, directly resolving the contradiction between current control and device scaling.
3Ease of manufacture
If conventional source/drain structures are used, then manufacturing process is simple, but device performance is limited
Solution Approach 1:
The patent changes the crystalline structure parameter of the semiconductor material films in the source/drain region. By depositing multiple layers with different crystalline structures (amorphous, polycrystalline, and monocrystalline), the patent optimizes device performance without fundamentally changing the manufacturing process flow. Each crystalline structure can be deposited using standard semiconductor techniques, maintaining ease of manufacture while the multi-layer crystalline structure provides enhanced carrier transport and reduced defect density, thereby improving device performance.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device comprises an active pattern on a substrate, the active pattern including a lower pattern that extends in a first direction, and sheet patterns that are spaced apart from the lower pattern in a second direction; a source/drain pattern on the lower pattern and in contact with the sheet patterns; and a gate structure on a side of the source/drain pattern, and including a gate insulating film and a gate electrode, wherein the source/drain pattern includes a first semiconductor material film in contact with each of the sheet patterns, a second semiconductor material film on the first semiconductor material film, and a third semiconductor material film on the second semiconductor material film, the first semiconductor material film has a monocrystalline structure, the second semiconductor material film has a polycrystalline structure, and the third semiconductor material film has an amorphous structure.