3D Multi-Bit Flip-Flop Cell Footprint Reduction
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Solution Overview
Problem
Conventional multi-bit flip-flops are large and consume high dynamic current, causing placement and routing challenges as well as strain on the power supply grid due to their size and resource sharing requirements.
Innovation Solution
Implementing a monolithic three-dimensional multi-bit flip-flop design that splits the circuit into two tiers, with clocked portions in one tier and non-clocked portions in another, sharing a common clock and scan circuit across both tiers to reduce cell footprint and alleviate routing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional multi-bit flip-flops share common resources (clock and scan circuitry), then power and area efficiency is improved, but cell size and dynamic current draw increase
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture, placing clocked portions in one tier and non-clocked portions in another tier above it. This vertical stacking reduces the cell footprint in the planar direction while maintaining all necessary functional components, effectively resolving the contradiction between area efficiency and cell size.
2Use of energy by moving object
If conventional multi-bit flip-flops share common resources (clock and scan circuitry), then power efficiency is improved, but dynamic current draw increases
Solution Approach 1:
The patent segments the multi-bit flip-flop into distinct clocked portions and non-clocked portions, with each having separate input/output structures. This segmentation allows for more granular control of signal paths and reduces unnecessary switching activity, thereby lowering dynamic current draw while preserving the power efficiency benefits of shared common resources.
3Ease of operation
If multi-bit flip-flops are placed in a single tier, then routing is simpler, but placement difficulty and routing congestion increase
Solution Approach 1:
By stacking clocked and non-clocked portions in different tiers, the patent reduces planar routing congestion. The vertical separation allows input and output structures to be distributed across tiers, shortening signal paths and reducing the complexity of routing in the planar direction, thereby easing both placement and routing challenges.
Data Source
AI summary
A 3D multi-bit flip-flop may include a two tier structure. The two tier structure may include a first tier containing a common clock circuit for the multi-bit flip-flop as well as the clock driven portions of the individual flip-flops and a second tier containing a common scan circuit for the multi-bit flip-flop as well as the non-clock driven portions of the individual flip-flops. Alternatively, the first tier may include the common clock circuit as well as a portion of the individual flip-flops and the second tier may include the common scan circuit as well as the other portion of the individual flip-flops.