3D NAND Stack Structure Asymmetric Electrodes Integration Density
Solution Overview
Problem
The integration density of two-dimensional semiconductor devices is limited by costly pattern formation techniques, necessitating the development of three-dimensional semiconductor memory devices with improved reliability and manufacturing methods.
Innovation Solution
A semiconductor memory device with a stack structure featuring horizontal electrodes and vertical structures, including a channel layer, tunneling insulating layer, charge storage layer, and blocking insulating layer, stacked on a substrate, along with a method of manufacturing that involves forming mold structures, etching, and replacing sacrificial layers with horizontal electrodes to enhance integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional planar semiconductor devices are used, then manufacturing cost is reduced, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar devices to three-dimensional vertical structures by stacking multiple horizontal electrodes and insulating layers vertically. The stack structure includes alternating layers of first and second horizontal insulating layers with first and second horizontal electrodes, creating a multi-layer vertical architecture that dramatically increases integration density while using standard manufacturing processes
2Quantity of substance
If three-dimensional stack structures are formed, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms alternating stacks of first horizontal insulating layers and second horizontal insulating layers before forming the electrodes. This preliminary layering creates a prepared template that simplifies subsequent electrode formation and alignment, reducing overall manufacturing complexity despite the three-dimensional structure
Solution Approach 2:
The stack structure is divided into repeating units of first horizontal insulating layers, second horizontal insulating layers, first horizontal electrodes, and second horizontal electrodes. This segmentation into modular layers allows for systematic manufacturing and simplifies the formation of complex three-dimensional structures through repeated patterning and deposition cycles
3Quantity of substance
If fine pattern techniques are used to increase integration density, then device performance is improved, but manufacturing cost increases
Solution Approach 1:
Instead of increasing integration density through finer lateral patterning, the patent achieves higher density by extending the structure into the vertical dimension with multiple stacked layers of electrodes and insulators. This vertical stacking approach maintains compatibility with existing manufacturing capabilities while dramatically increasing the number of memory cells per chip area
4Quantity of substance
If horizontal electrodes are extended in extension regions, then charge storage capacity is improved, but structural complexity increases
Solution Approach 1:
The patent creates asymmetric electrode structures where second horizontal electrodes in extension regions extend further than first horizontal electrodes, while first horizontal electrodes extend further in cell array regions. This asymmetric design optimizes charge storage capacity in different functional regions without requiring completely different manufacturing processes for each region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution increases integration density and reliability of semiconductor memory devices by enabling the formation of complex three-dimensional structures that overcome the limitations of two-dimensional devices, while simplifying the manufacturing process and reducing material loss.
Implementation Method 1
a tunneling insulating layer, a charge storage layer and a blocking insulating layer, which are sequentially stacked on a sidewall of the channel layer
Data Source
AI summary
A semiconductor memory device includes a stack structure comprising horizontal electrodes sequentially stacked on a substrate including a cell array region and an extension region and horizontal insulating layers between the horizontal electrodes. The semiconductor memory device may further include vertical structures that penetrate the stack structure, a first one of the vertical structures being on the cell array region and a second one of the vertical structures being on the extension region. Each of the vertical structures includes a channel layer, and a tunneling insulating layer, a charge storage layer and a blocking insulating layer which are sequentially stacked on a sidewall of the channel layer. The charge storage layer of the first vertical structure includes charge storage patterns spaced apart from each other in a direction perpendicular to a top surface of the substrate with the horizontal insulating layers interposed therebetween. The charge storage layer of the second vertical structure extends along sidewalls of the horizontal electrodes and sidewalls of the horizontal insulating layers.