3D NAND Block Cut Layout for Dense, Reliable Memory Arrays

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Solution Overview

Problem

The integration of two-dimensional semiconductor memory devices is limited due to the need for expensive miniaturization techniques, and three-dimensional structures are needed to enhance integration without increasing costs.

Innovation Solution

A semiconductor memory device with a stacked structure featuring vertical channel and block cut structures, including inter-electrode insulating films and gate electrodes, which allows for increased integration and improved reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If two-dimensional semiconductor memory devices use expensive miniaturization techniques to increase integration, then integration density improves, but manufacturing cost increases

Engineering Contradiction:
Improveintegration densityVSAvoidmanufacturing cost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent transitions from two-dimensional planar memory cells to three-dimensional stacked structures with vertical channel structures extending through multiple memory cell layers. This dimensional change allows integration density to increase without requiring further miniaturization of individual cell components, thereby avoiding the need for expensive advanced lithography equipment while achieving higher capacity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The memory device is divided into multiple stacked memory cell layers separated by inter-electrode insulating films, with each layer containing channel structures, word lines, and bit lines. This segmentation into discrete functional layers enables independent optimization and manufacturing of each layer, simplifying the overall manufacturing process compared to miniaturizing a single planar layer.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If three-dimensional stacked structures are implemented to increase integration, then manufacturing cost decreases, but device reliability may worsen due to structural complexity

Engineering Contradiction:
Improvemanufacturing costVSAvoiddevice reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

Inter-electrode insulating films are inserted between adjacent memory cell layers to provide electrical isolation and prevent interference between stacked structures. These insulating layers act as protective barriers that cushion against potential electrical breakdown or leakage paths, thereby maintaining reliability despite the increased structural complexity of the three-dimensional stacked configuration.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The inter-electrode insulating films serve as intermediary layers between the conductive elements of adjacent memory cell layers. These intermediary insulating structures mediate the interaction between stacked layers, preventing direct electrical contact and potential short circuits, thus ensuring reliable operation of the three-dimensional memory device.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If block cut structures are used to define block regions, then manufacturing precision improves, but device complexity increases

Engineering Contradiction:
Improveblock region definitionVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The block cut structures serve multiple functions: they define block regions for selective memory operations, provide physical separation between functional blocks, and act as etch stop layers during manufacturing processes. This multi-functionality reduces the need for additional dedicated structures, thereby limiting the increase in device complexity while achieving precise block region definition.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The block cut structures are merged with the existing vertical channel structures and inter-electrode insulating films, combining multiple functions into unified structural elements. This merging approach achieves precise block region definition without adding separate dedicated structures, thereby minimizing the increase in overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12532469B2Semiconductor memory device and electronic system including the same
Publication Date: 2026.01.20 SAMSUNG ELECTRONICS CO LTD
  • US12532469B2 patent drawing
  • US12532469B2 patent drawing
  • US12532469B2 patent drawing

AI summary

A semiconductor memory device may include a substrate including a first and a second block region, and a stacked structure including insulating films and gate electrodes alternately stacked on the substrate. A vertical channel structure, a word line cut structure, and a block cut structure may penetrate the stacked structure. The word line cut structure may extend in a second direction. The block cut structure may extend in a first direction, connect to the word line cut structure, and define the first and second block regions. The block cut structure may include a first portion connected to the word line cut structure and a second portion connected to the first portion. From a planar viewpoint, the first portion may include at least a part not overlapping the second portion in the first direction and at least a region not overlapping the word line cut structure in the first direction.