3D NAND Page Buffer Control for Layer-Specific Reliability
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Solution Overview
Problem
Existing 3D nonvolatile memory devices face challenges in maintaining reliability due to characteristic differences between memory cells formed in different layers, which affect word line and bit line loading, leading to inconsistent performance.
Innovation Solution
The memory device independently controls page buffers and word lines for each layer, adjusting operation conditions such as voltage levels and application times based on layer-specific characteristics to compensate for these differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are formed in multiple stacked layers to increase capacity, then storage density is improved, but characteristic differences between layers cause unreliable core operations
Solution Approach 1:
The page buffer circuit is divided into multiple independent page buffer groups, with each group assigned to control a specific layer. This segmentation allows each page buffer group to independently manage its associated layer's word lines and bit lines, enabling layer-specific operation optimization without affecting other layers, thus resolving the reliability issue caused by layer characteristic differences while maintaining high storage capacity
Solution Approach 2:
Each page buffer group is configured with local control capabilities specific to its assigned layer, allowing independent adjustment of operation parameters (such as voltage levels and timing) according to the characteristic requirements of each layer. This local quality approach ensures that each layer operates under optimal conditions tailored to its specific characteristics, improving overall system reliability
2Reliability
If independent control of page buffers for each layer is implemented, then core operation reliability is improved, but device complexity increases
Solution Approach 1:
The control logic circuit is segmented into multiple independent page buffer groups, where each group manages a specific layer. This segmentation distributes the control complexity across multiple manageable units rather than requiring a single complex control unit, making the overall system easier to design, implement, and maintain while achieving independent layer control
Solution Approach 2:
Each page buffer group is designed with universal functionality to handle multiple operations (read, program, erase) for its assigned layer using a standardized control structure. This multi-functionality reduces the need for separate dedicated circuits for each operation type, thereby controlling device complexity while maintaining reliable independent control across layers
Data Source
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AI summary
A memory device is provided. The memory device includes: a memory cell array including a first string provided in a first layer (CL1) and a second string (STR1_C2) provided in a second layer (CL2) stacked on the first layer (CL1); a page buffer circuit (1140) including a first page buffer (PB1) corresponding to the first string of the first layer and a second page buffer (PB2) corresponding to the second string (STR1_C2) of the second layer; and a control logic circuit (1170) configured to control the first page buffer (PB1) and the second page buffer (PB2) independently, in a core operation.