3D NAND Memory Built-In Capacitor Power Failure Protection

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Solution Overview

Problem

Traditional memory sub-systems face inefficiencies in managing power loss events due to the need for large capacitors on printed circuit boards, which consume physical real estate and reduce storage capacity.

Innovation Solution

Incorporating a built-in capacitor within memory components, such as between strings of memory cells, to provide holdup power during power failures, allowing for completion of operations and reducing the need for external capacitors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If large capacitors are used on printed circuit boards to manage power loss events, then power failure protection is improved, but physical real estate is consumed and storage capacity is reduced

Engineering Contradiction:
Improvepower failure protectionVSAvoidphysical real estate
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines the capacitor function with the memory device structure by forming capacitors using the bit line structures and insulating layers within the memory array itself. This integration merges the power management function into the storage device, eliminating the need for separate external capacitors on the printed circuit board.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The invention transitions from a two-dimensional PCB layout to a three-dimensional integrated structure by forming capacitors vertically within the memory device layers. The capacitors are constructed using stacked layers of conductive bit lines and insulating materials, utilizing the vertical dimension to provide holdup power without consuming additional planar space.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If large capacitors are used on printed circuit boards to manage power loss events, then power failure protection is improved, but storage capacity is reduced

Engineering Contradiction:
Improvepower failure protectionVSAvoidstorage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent combines the capacitor function with the memory device structure by forming capacitors using the bit line structures and insulating layers within the memory array itself. This integration merges the power management function into the storage device, eliminating the need for separate external capacitors on the printed circuit board.

Inventive Principle:
Principle #5Merging (Combining)

3Quantity of substance

If built-in capacitors are integrated within memory components, then physical space is freed up and storage capacity is enhanced, but device complexity increases

Engineering Contradiction:
Improvestorage capacityVSAvoiddevice complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The bit line structures serve dual functions: as conductive interconnects for memory cell access and as electrode structures for capacitor formation. The insulating layers between bit lines serve both as electrical isolation for memory operations and as dielectric material for capacitor functionality, reducing the need for additional dedicated components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention changes the functional parameters of existing structures by reconfiguring the electrical characteristics of bit lines and insulating layers. By adjusting voltage potentials and electrical connections during power loss events, the same physical structures provide both memory access and energy storage functions without adding structural complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution ensures optimal performance and prevents data loss while freeing up physical space for additional memory components, enhancing overall efficiency and storage capacity.

Implementation Method 1

a slit portion comprising a capacitor in which a first metal portion of the capacitor is adjacent to the first units of linearly arranged strings of memory cells and a second metal portion of the capacitor is adjacent to the second units of linearly arranged strings of memory cells

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS12170117B23D NAND memory with built-in capacitor
Publication Date: 2024.12.17 MICRON TECHNOLOGY INC
  • US12170117B2 patent drawing
  • US12170117B2 patent drawing
  • US12170117B2 patent drawing

AI summary

An apparatus that includes a set of memory components of a memory sub-system is provided. The set of memory components include a first memory block comprising first units of linearly arranged memory cells and a second memory block comprising second units of linearly arranged memory cells. The set of memory components include a slit portion dividing the first and second memory blocks. The slit portion includes a capacitor in which a first metal portion of the capacitor is adjacent to the first units of linearly arranged memory cells and a second metal portion of the capacitor is adjacent to the second units of linearly arranged memory cells.