3D NAND Flash Memory Cell Isolation via Segmented Charge Storage
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Solution Overview
Problem
Current three-dimensional NAND flash memory experiences interference phenomena between memory cells due to continuous charge storage structures, which affects the degree of integration and area utilization.
Innovation Solution
A three-dimensional non-volatile memory design featuring a stacked structure with alternating first dielectric layers and gates, where charge storage structures are isolated by a first dielectric layer, comprising a sequence of first oxide, nitride, and second oxide layers, and a channel layer on the sidewall, with optional buffer and barrier layers to improve cell isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If charge storage structures are connected continuously to enhance integration, then degree of integration is improved, but interference phenomenon between memory cells increases
Solution Approach 1:
The continuous charge storage structure is segmented into discrete units by introducing first dielectric layers between adjacent charge storage structures. This segmentation isolates individual memory cells, preventing interference while maintaining high integration through the three-dimensional stacked configuration.
Solution Approach 2:
The first dielectric layer acts as an intermediary substance inserted between adjacent charge storage structures. This dielectric medium provides electrical isolation and prevents charge leakage or interference between neighboring memory cells, enabling continuous operation without cross-talk.
2Object-generated harmful factors
If dielectric layers are inserted to isolate charge storage structures to reduce interference, then interference phenomenon is reduced, but device complexity increases
Solution Approach 1:
The first dielectric layer is merged with the gate dielectric layer in the stacked structure, combining multiple functions into a single integrated layer. This approach isolates charge storage structures while maintaining the alternating stack configuration, thereby reducing interference without proportionally increasing device complexity.
Solution Approach 2:
The first dielectric layer serves multiple functions simultaneously: it acts as an isolation layer between charge storage structures, provides gate dielectric functionality in the stacked configuration, and enables continuous formation through standard dielectric deposition processes. This multi-functionality reduces the need for additional specialized layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces interference between memory cells, enhancing the integration and operational efficiency of three-dimensional NAND flash memory by isolating adjacent charge storage structures with a dielectric layer.
Implementation Method 1
Two adjacent charge storage structures are isolated by the first dielectric layer therebetween
Data Source
AI summary
A three-dimensional non-volatile memory including a substrate, a stacked structure and a channel layer. The stacked structure is disposed on the substrate and includes first dielectric layers, gates and charge storage structures. The first dielectric layers and the gates are alternately stacked. The charge storage structures are disposed at one side of the gates. Two adjacent charge storage structures are isolated by the first dielectric layer therebetween. Each of the charge storage structures includes a first oxide layer, a nitride layer and a second oxide layer sequentially disposed at one side of each of the gates. The channel layer is disposed on a sidewall of the stacked structure adjacent to the charge storage structures.