3D NAND Charge Storage Layout for Cell Interference Control
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Solution Overview
Problem
Three-dimensional NAND flash memory requires high reliability to maintain performance and durability, but existing technologies face challenges in achieving this.
Innovation Solution
A semiconductor memory device with a specific structure comprising alternating layers of insulating and gate electrode layers, including charge storage layers with unique shapes and distances, enhances reliability by optimizing charge storage and control electrode configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional NAND flash memory structure is used to achieve high integration, then storage capacity increases, but reliability deteriorates due to increased complexity and potential interference
Solution Approach 1:
The gate electrode layer is segmented into multiple regions (first region, second region, third region) along the first direction, with charge storage layers positioned at different distances from each region. This segmentation allows independent control and optimization of charge storage for each gate electrode region, reducing interference between adjacent memory cells while maintaining high integration density.
Solution Approach 2:
Different charge storage layers are positioned at different distances from the gate electrode layer in different regions. Specifically, the first charge storage layer is at a first distance from the first gate electrode layer, the second charge storage layer is at a second distance from the second gate electrode layer, and the third charge storage layer is at a third distance from the third gate electrode layer. This local quality variation optimizes charge storage and reduces interference between adjacent cells, thereby improving reliability while maintaining high storage capacity.
2Reliability
If charge storage layers are positioned closer to gate electrode layers to improve charge storage efficiency, then data retention improves, but interference between adjacent cells increases
Solution Approach 1:
The gate electrode layer is divided into multiple separated regions along the first direction, with charge storage layers positioned at optimized distances from each region. This segmentation creates isolated charge storage zones that prevent charge leakage and interference between adjacent memory cells while maintaining efficient charge storage for data retention.
Solution Approach 2:
Each charge storage layer is positioned at a specific optimized distance from its corresponding gate electrode layer region. This local optimization ensures that charge storage is maximized for each cell while the spatial separation prevents harmful electromagnetic interference between adjacent cells, resolving the contradiction between data retention and interference reduction.
3Productivity
If gate electrode layers are densely packed to increase integration density, then storage capacity increases, but control precision deteriorates
Solution Approach 1:
The gate electrode layer is segmented into multiple distinct regions along the first direction, allowing each region to be independently controlled. This segmentation enables precise control of charge storage in each memory cell even when cells are densely packed, maintaining control precision while increasing integration density.
Solution Approach 2:
The patent utilizes the first direction (vertical stacking direction) to arrange multiple gate electrode layers and charge storage layers at different heights and positions. This three-dimensional arrangement allows dense integration while maintaining precise control over charge storage in each cell through vertical and horizontal positioning, effectively using dimensional space to resolve the density-precision trade-off.
Data Source
AI summary
A semiconductor memory device includes a first semiconductor layer, a first gate electrode layer, a second gate electrode layer including a first region and a second region that is separated from the first region, the first semiconductor layer being provided between the first region and the second region, a third gate electrode layer that is provided between the first gate electrode layer and the second gate electrode layer, and includes a third region and a fourth region that is separated from the third region, the first semiconductor layer being provided between the third region and the fourth region, a first charge storage layer provided between the first semiconductor layer and the first gate electrode layer, and having an annular shape, a second charge storage layer provided between the first semiconductor layer and the second region, and having a horseshoe shape, and a third charge storage layer provided between the first semiconductor layer and the fourth region, and having a horseshoe shape. A first distance from an end of the second region to an end of the second charge storage layer is greater than a second distance from an end of the fourth region to an end of the third charge storage layer.