3D-NAND Charge Trap Segmentation for Lower Cell Interference
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Solution Overview
Problem
Current 3D-NAND devices face issues with cell-to-cell interference and lateral charge spreading due to a continuous charge trap layer, hindering the scale-down of word line to word line insulators, and existing trap-cut structures are problematic for gate area usage and shape/thickness variation.
Innovation Solution
A 3D-NAND structure with a discontinuous charge trap layer is fabricated using atomic layer deposition of silicon nitride, confined between tunnel oxide and word lines, and a trap-cut method to eliminate interference and spreading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a continuous charge trap layer is used, then storage capacity is improved, but cell-to-cell interference and lateral charge spreading increase
Solution Approach 1:
The continuous charge trap layer is segmented into discrete charge trap regions separated by blocking oxide layers. Each memory cell has its own confined charge trap layer that is spatially isolated from adjacent cells, preventing charge leakage and interference while maintaining sufficient storage capacity within each cell region.
Solution Approach 2:
The harmful continuous charge trap layer is extracted and replaced with discrete charge trap regions. The blocking oxide layers are introduced to remove the harmful connectivity between cells, extracting only the necessary charge storage function while eliminating the interference problem.
2Quantity of substance
If a continuous charge trap layer is used, then storage capacity is improved, but lateral charge spreading increases
Solution Approach 1:
The charge trap layer is segmented into discrete regions laterally separated by blocking oxide layers. This segmentation confines charges to vertical regions beneath each word line and bit line intersection, preventing lateral spreading while maintaining storage capacity through vertical stacking.
Solution Approach 2:
Different regions of the structure have different properties: charge trap layers in active memory cell regions have high charge storage capability, while regions between cells have blocking oxide layers with high resistance to charge transport. This local differentiation enables storage where needed while preventing spreading in between.
3Object-affected harmful factors
If a trap-cut structure is used to eliminate interference, then cell-to-cell interference is reduced, but gate area usage decreases
Solution Approach 1:
Instead of using horizontal trap-cut structures that reduce gate area, the patent uses vertical blocking oxide layers to achieve isolation. The blocking occurs in the vertical dimension between charge trap layers, allowing full utilization of the horizontal gate area for memory cell formation.
4Object-affected harmful factors
If a trap-cut structure is used to eliminate interference, then cell-to-cell interference is reduced, but shape and thickness variation increases
Solution Approach 1:
The problematic trap-cut process is replaced by extracting and introducing blocking oxide layers through oxidation. This oxidation process naturally conforms to the underlying topology and provides self-aligned isolation, reducing shape and thickness variation compared to mechanical trap-cut methods.
Solution Approach 2:
The blocking oxide layer acts as an intermediary material that provides isolation without requiring precise mechanical cutting. The oxidation process serves as a self-regulating intermediary step that automatically adapts to underlying features, reducing manufacturing precision requirements compared to direct trap-cut methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces cell-to-cell interference and lateral charge spreading, enabling scale-down of 3D-NAND devices by using a confined charge trap layer that maintains consistent shape and thickness.
Implementation Method 1
oxidizing a portion of the second material adjacent the memory hole to form a blocking oxide layer
Implementation Method 2
A 3D-NAND structure with a discontinuous charge trap layer is fabricated using atomic layer deposition of silicon nitride
Data Source
AI summary
Described is a memory device including a plurality of memory cells formed around a memory hole extending through a memory stack on a substrate. Each of the plurality of memory cells comprises a discrete blocking oxide layer, a charge trap layer, and a tunnel oxide layer. The blocking oxide layer is discrete between each of the plurality of memory cells. The tunnel oxide layer is continuous between each of the plurality of memory cells, and the charge trap layer is discrete between each of the plurality of memory cells. The charge trap layer has a first thickness on a top portion and a second thickness on a center portion, the first thickness different than the second thickness.