3D NAND Memory Common Bit Line Merging
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Solution Overview
Problem
Current three-dimensional non-volatile memory devices, such as vertical NAND strings, face challenges in efficiently forming monolithic memory arrays with high density and reliable operation due to complexities in stacking and interconnectivity of memory layers.
Innovation Solution
The formation of a monolithic three-dimensional NAND string memory device involves an alternating stack of insulating and sacrificial material layers, where sacrificial layers are replaced with conductive electrodes, and ion implantation is used to create selectively doped channel regions, enabling efficient memory cell formation and interconnectivity within a single substrate without intervening layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple NAND strings are formed in a memory block, then memory density is improved, but the number of bit lines required increases leading to increased device complexity
Solution Approach 1:
Multiple NAND strings (first, second, third, and fourth NAND strings) are merged to share a single common bit line. The bit line formation process creates one continuous conductive structure that electrically connects to multiple drain regions across different memory blocks, eliminating the need for separate bit lines for each NAND string and reducing overall device complexity while maintaining high memory density
Solution Approach 2:
The common bit line serves multiple functions simultaneously: it acts as a bit line for multiple different memory blocks (first, second, third, and fourth memory blocks), enabling a single structure to handle data transfer for multiple NAND strings. This multi-functionality reduces the total number of bit lines required and simplifies the interconnect architecture
2Manufacturing precision
If ion implantation is used to create doped channel regions, then manufacturing precision is improved, but the manufacturing process complexity increases
Solution Approach 1:
Ion implantation is performed at predetermined stages during the fabrication process to create doped channel regions in specific locations (first and second doped channel regions in the first semiconductor channel, third and fourth doped channel regions in the second semiconductor channel). This preliminary doping action ensures precise control over channel characteristics before subsequent processing steps, improving manufacturing precision while integrating seamlessly into the overall fabrication flow
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of high-density, reliable monolithic memory arrays with improved operational efficiency and reduced complexity in manufacturing, enhancing the performance and scalability of three-dimensional memory devices.
Implementation Method 1
ion implantation is used to create selectively doped channel regions
Data Source
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AI summary
Two vertical NAND strings can share a common bit line by providing two pairs of drain select transistors. Channels of each vertical NAND string containing an adjoining pair of drain select transistors are incorporated into a respective vertical semiconductor channel, which is adjoined to a respective drain region which is connected to the common bit line. The drain select transistors have mismatched threshold voltages at each level such that each vertical NAND string includes a level at which a respective drain select transistor has a higher threshold voltage than a counterpart drain select transistor for the other vertical NAND string at the same level. By turning on three drain select transistors out of four, only one vertical NAND string can be activated while the common bit line is biased at a suitable bias voltage. A programming operation or a read operation can be performed only on the activated NAND string.