Read-Only Memories TRIZ Cases

Detrap voltage increases channel potential to inject holes for removing trapped electrons, stabilizing threshold voltage during program operations.

Ion implantation and programming adjust drain select transistor thresholds to narrow distribution spread.

A memory controller restores verification results after suspending program operations to maintain data integrity.

Parallel folded stages cancel spurious capacitive currents, enabling fast memory cell state reading without waiting for transient decay.

Delaying dummy word line voltage ramp-up reduces channel gradients and threshold voltage disturbs in 3D NAND memory strings.

A BIST module generates test addresses autonomously to execute memory procedures without external command dependence.

Calculating threshold voltage distribution parameters allows a memory controller to dynamically adjust reference voltages, reducing error rates caused by aging.

Dynamic voltage adjustment compensates for signal degradation across memory arrays, reducing raw bit error rates.

A sensing circuit uses a single transistor to charge and detect voltage levels for precise memory state determination.

Matching the sense amplifier configuration with SRAM cells resolves low-voltage defects and boosts manufacturing yield.

A flash memory apparatus allocates status bits in spare sectors to track write progress and determine sector validity.

Dynamic pass voltage adjustment counters unselected word line coupling to maintain threshold voltage sensing accuracy and prevent read disturbance.

Sidewalls form potential wells that enhance charge trapping, resolving alignment precision issues during device miniaturization.

Segmented drilling and plating establishes layer alignment before lamination to maintain signal integrity.

Stacked PMOS and NMOS transistors supply reference voltages through segmented circuits.

Constant-voltage write operations using a voltage holding section prevent adverse effects on magnetoresistive elements while enabling high-speed switching.

Negative threshold voltages expand the storage axis to increase density while reducing operating voltage and interference.

A controller characterizes non-volatile memory erase blocks by programming and verifying contiguous page sequences to identify instability points.

Segmented antifuse voltage generator boosts programming voltage while reducing circuit size and improving layout flexibility.

A charge-trapping memory cell incorporates carbon, boron, phosphorus, or metal additives into the silicon nitride layer to modify trap depths.

Dynamic pad reconfiguration routes training data through existing pins, maintaining device size while improving reliability.

A regulator stage filters ripple from charge-pump outputs to stabilize word line biasing in non-volatile memory arrays.

Segmented voltage generation blocks apply address-dependent precharge levels to the main bit line, reducing propagation delay for distant memory cells.

A memory controller selects enhanced write pulses based on prior read counts to maintain data integrity.

Measures unselected cell resistance to dynamically adjust read thresholds, correcting threshold voltage shifts caused by the back pattern effect.

Iterative calibration updates read level offsets to prevent threshold voltage shifts from exceeding error correction capacity.

A memory controller calculates word line access frequencies to identify aggressor addresses and replaces their cells with backup lines.

Anti-fuse elements and switch units in a programmable memory cell reduce area occupation and enhance reading speed.

Segmented bit line activation reduces peak and average current consumption while maintaining programming speed and verification accuracy.

Sensing circuits detect channel-to-floating gate capacitive coupling to set compensating bit line voltages, preventing threshold voltage distribution widening.

A semiconductor memory device segments arrays into multilevel and single-level regions to distribute write operations across parallel data caches.

Grouping memory blocks into super blocks allows storing successful read levels in a history buffer, reducing read retry operations caused by cell degradation.

Elongated continuous active region with an isolation transistor between pass transistors.

A multi-level cell programming method applies inhibit and zero voltage conditions to bit lines to reduce adjacent line voltage swings.

Merged vertical NAND strings share a single bit line to reduce interconnect complexity while maintaining high memory density.

A resistance change memory design configures MOS transistors in cutoff states during standby periods to minimize power consumption.

A memory controller selects candidate data sets with the fewest vulnerable cells to store in non-volatile memory regions.

Complementary memory cell configuration eliminates external terminals by applying power-supply voltage to control gates for internal threshold detection.

Controller selects write target blocks based on fail bit counts to prevent bad block formation from uneven erase operations.

A memory controller uses redundant fuse circuits to identify and replace deteriorated memory blocks with spare units.

A flexible decoder generates programmable selection signals to identify optimal reference cells within a memory array.

A differential current sensing circuit reads preprogrammed nonvolatile memory cells using cross-coupled inverters and controlled current sources.

A data storage circuit uses separate antifuses for data and initialization states to manage node voltage levels.

Control logic applies voltages to bit lines and GIDL lines to suppress deep erase cells during verification cycles.

A memory cell system measures electron discharge time to store multiple bits in a single device.

A nonvolatile memory array employs bipolar programmable resistance storage elements connected to word, bit, and source lines.

Tracks program/erase cycles and narrows voltage pulses to reduce intermediate state ambiguity and lower write error probability.