Differential Current Sensing for Preprogrammed NVM Cells
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Solution Overview
Problem
Conventional sensing techniques for non-volatile memory (NVM) cells are inefficient for reading pre-programmed states and detecting faults, as they require multiple cycles and cannot utilize differential current sensing like SRAM integrated circuits, which are not applicable due to the absence of programmed and unprogrammed cell pairs.
Innovation Solution
An integrated circuit sensing circuit architecture using cross-coupled inverters and current sources/sinks to perform differential current sensing between bitlines, allowing for the reading of selected and complementary memory cells prior to programming, with a method involving two cycles to detect faults by alternating connections and sensing currents through bitlines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional single-ended sensing technique is used for reading pre-programmed NVM cells, then the sensing can be performed, but the sensing speed is slow and multiple cycles are required
Solution Approach 1:
The patent merges the sensing of selected and complementary memory cells into a single differential sensing operation. By connecting both bit line and complementary bit line to a shared sense amplifier and performing differential sensing simultaneously, the patent eliminates the need for separate sensing cycles, thereby improving sensing speed and reducing time loss.
Solution Approach 2:
The patent employs periodic switching of current sources/sinks to enable differential sensing operations. By alternately activating current sources on different bit lines in a periodic manner, the system can perform fast differential sensing while maintaining the ability to read both selected and complementary cells within a single cycle framework.
2Speed
If differential current sensing technique from SRAM is applied to pre-programmed NVM cells, then sensing speed improves, but the technique cannot be directly used because there are no programmed and unprogrammed cell pairs
Solution Approach 1:
The patent introduces dynamic control elements (switches and controllable current sources/sinks) that allow the sensing circuit to adapt its operation mode. By dynamically activating current sources based on whether the cell is programmed or unprogrammed, the system can perform differential sensing on pre-programmed cells even though they lack complementary programmed/unprogrammed pairs, thus achieving both speed improvement and adaptability.
Solution Approach 2:
The patent changes the operational parameters of the sensing circuit by introducing controllable current sources/sinks that can be activated or deactivated based on the cell state. This parameter control enables the differential sensing technique to work with pre-programmed cells by artificially creating the current differential that would normally exist only between programmed and unprogrammed cell pairs.
3Reliability
If two-cycle sensing method is used for pre-programmed cells with alternating bit line connections, then cell integrity can be checked, but the sensing process is time-consuming
Solution Approach 1:
The patent combines the integrity checking function with the normal read operation by performing differential sensing on both selected and complementary cells simultaneously within a single cycle. The controllable current sources/sinks enable the circuit to detect abnormalities in both cells at the same time, maintaining reliability while reducing the time required compared to sequential two-cycle sensing.
Data Source
AI summary
A differential current sensing circuit architecture is used with an integrated circuit NVM memory block in which a selected memory cell and a related complementary memory cell are accessed at the same time for reading. The circuit architecture is used not only for normal operations for reading the logic states of a selected memory cell and its complementary memory cell after programming, but also for reading the logic states of a selected memory cell and its complementary memory cell before programming for the detecting of faults in memory cells.