Memory Subsystem Autocal Error Recovery
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Solution Overview
Problem
Flash memory devices, particularly NAND-based, face bit errors due to shifts in threshold voltages over time, which can exceed the correction capacity of error correcting codes, leading to unreadable data states and reduced memory device efficiency.
Innovation Solution
Implementing a walking read level calibration system that uses calibration circuitry to iteratively measure and adjust read level signals, accounting for shifts in threshold voltages, thereby updating read level signals to maintain data accuracy and extend memory device lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correcting code (ECC) techniques are employed to detect and correct bit errors, then data accuracy is improved, but the correction capacity is limited and eventually exceeded as threshold voltages shift over time
Solution Approach 1:
The patent performs read level calibration before actual data reading operations to proactively adjust read levels based on threshold voltage shifts. This preliminary calibration prevents bit errors from occurring in the first place, rather than relying solely on ECC to correct errors after they occur. The calibration process measures performance characteristics and determines offset values that are applied to adjust read levels, thereby maintaining data accuracy within the ECC correction capacity.
2Productivity
If multiple erase and write cycles are performed to increase storage usage, then storage capacity utilization is improved, but threshold voltages shift causing bit errors that exceed ECC correction capacity
Solution Approach 1:
The patent implements periodic read level calibration operations at defined intervals (e.g., after a certain number of erase/write cycles or at predetermined time intervals). This periodic calibration maintains threshold voltage compensation over the lifespan of the memory device, ensuring that data readability is preserved even as storage capacity utilization increases through multiple erase and write cycles. The calibration process is repeated periodically to adapt to ongoing threshold voltage shifts.
3Ease of operation
If read level signals are kept fixed to simplify operations, then ease of operation is improved, but threshold voltage shifts cause bit errors reducing memory device efficiency
Solution Approach 1:
The patent implements an automatic calibration system that self-adjusts read levels without requiring manual intervention. The calibration circuitry automatically measures performance characteristics of the memory device, determines appropriate offset values, and applies corrections to read level signals. This self-service approach maintains ease of operation while improving memory device efficiency, as the system autonomously compensates for threshold voltage shifts without burdening the user with complex calibration procedures.
4Measurement precision
If calibration is performed frequently to maintain accuracy, then data accuracy is improved, but processing time and system complexity increase
Solution Approach 1:
The patent performs calibration on selected portions of the memory device rather than the entire device, and only when necessary based on predefined criteria. The calibration process targets specific memory regions that exhibit threshold voltage shifts, applying corrections only where needed. This partial action approach maintains read level accuracy while minimizing calibration time and avoiding unnecessary processing of memory regions that do not require calibration.
Data Source
AI summary
Several embodiments of memory devices and systems with walking read level calibration are disclosed herein. In one embodiment, a system includes a memory component having at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to perform iterative calibrations of the memory region by determining a first read level offset value during a first calibration. A new base read level test signal is determined based on the first read level offset value. During a second calibration using the new base read level test signal, a second read level offset value is determined.