Semiconductor Memory Pad Reconfiguration for Training Data Synchronization

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Solution Overview

Problem

There is an increasing demand for improved performance and reliability in semiconductor memory devices without increasing the number of pads, which would otherwise lead to larger size and higher manufacturing costs.

Innovation Solution

The semiconductor memory device includes a memory core with data delivery and training blocks connected between pads, allowing for synchronized output of training data through different pads, enabling efficient communication and training operations without additional pads, thereby improving reliability and reducing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If new pads are used for additional functions, then the functionality and reliability of semiconductor memory are improved, but the number of pads increases leading to larger size and higher manufacturing costs

Engineering Contradiction:
ImprovereliabilityVSAvoidnumber of pads
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies multi-functionality by enabling existing pads to serve multiple purposes. Specifically, pads originally designed for data input/output operations are configured to also handle training data transmission. The controller and memory device switch pad functions between operational modes (data transfer vs. training), allowing the same physical pads to fulfill different roles without requiring additional dedicated pads for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements dynamic functionality where pads can change their operational role based on the current mode. During normal operations, pads function as data I/O channels; during training operations, the same pads are dynamically reconfigured to transmit training data. This dynamic switching capability allows the system to adapt pad functions in real-time, eliminating the need for static dedicated pads for each function type.

Inventive Principle:
Principle #15Dynamics

2Reliability

If the number of pads is increased to support new functions, then the performance and reliability are improved, but the manufacturing cost increases

Engineering Contradiction:
ImprovereliabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent reduces manufacturing costs by eliminating the need for additional dedicated pads. By making existing pads multi-functional (serving both data I/O and training purposes), the design avoids the cost of adding more pads, reducing material usage, simplifying the manufacturing process, and lowering overall production expenses while maintaining the required functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If additional pads are added for training operations, then the training effectiveness is improved, but the device size increases

Engineering Contradiction:
Improvetraining effectivenessVSAvoiddevice size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent maintains compact device size by reusing existing pads for training operations. Instead of adding separate dedicated pads for training data transmission, the system configures the controller and memory device to use the same pads that handle data I/O operations. This approach preserves the original device footprint while enabling effective training functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUSRE49467E1Semiconductor memory devices, memory systems including semiconductor memory devices, and operating methods of semiconductor memory devices
Publication Date: 2023.03.21 SAMSUNG ELECTRONICS CO LTD
  • USRE49467E1 patent drawing
  • USRE49467E1 patent drawing
  • USRE49467E1 patent drawing

AI summary

A semiconductor memory device includes a memory core that performs reading and writing of data, data delivery and training blocks that are connected between first pads and the memory core, and at least one data delivery, clock generation and training block that is connected between at least one second pad and the memory core. In a first training operation, the data delivery and training blocks output first training data, received through the first pads, through the first pads as second training data. In a second training operation, at least one of the data delivery and training blocks outputs third training data, received through the at least one second pad, through at least one of the first pads as fourth training data. The second training data and the fourth training data are output in synchronization with read data strobe signals output through the at least one second pad.