Memory Device Redundant Fuse Circuit Bad Block Replacement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory cells deteriorate after cycling operations, leading to reduced reliability and increased erase and program times, with worn-out bits being difficult to correct, causing issues like increased wafer size, decreased operating speed, and higher power consumption.
Innovation Solution
A memory device with a memory cell array, redundant fuse circuit, and memory controller that records repair information including repair addresses, first enable bits, and second enable bits to identify and disable bad memory blocks, replacing them with redundant blocks to maintain performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes are used to correct damaged bits, then reliability is improved, but device complexity, operating speed, and power consumption increase
Solution Approach 1:
The memory device is segmented into regular memory blocks and redundant memory blocks. When a regular memory block deteriorates, it can be replaced by a corresponding redundant block. This segmentation allows the system to maintain reliability without requiring complex error correction codes across the entire memory device.
Solution Approach 2:
The patent implements a mechanism where deteriorated regular memory blocks are discarded (replaced) with redundant memory blocks. The redundant blocks serve as backup resources that can be activated when needed, effectively recovering the memory device's functionality without complex correction algorithms.
2Reliability
If error correction codes are used to correct damaged bits, then reliability is improved, but operating speed decreases
Solution Approach 1:
Redundant memory blocks are prepared in advance as backups for each regular memory block. When a regular block deteriorates, the replacement can occur quickly by activating the pre-prepared redundant block, avoiding time-consuming error correction processes during operation.
Solution Approach 2:
Instead of using time-consuming error correction codes, the system quickly replaces deteriorated blocks with pre-configured redundant blocks, maintaining high operating speed while ensuring reliability.
3Reliability
If error correction codes are used to correct damaged bits, then reliability is improved, but power consumption increases
Solution Approach 1:
The memory system is divided into regular and redundant segments, allowing targeted replacement of only the deteriorated portions. This avoids the continuous power consumption required by error correction codes that would need to operate across the entire memory device.
Solution Approach 2:
The system replaces deteriorated blocks with redundant blocks rather than continuously applying power-intensive error correction algorithms, thereby maintaining reliability with lower power consumption.
4Reliability
If redundant memory blocks are added to replace bad blocks, then reliability is improved, but device complexity increases
Solution Approach 1:
The memory device is organized into regular memory blocks and corresponding redundant memory blocks. Each redundant block is specifically paired with a regular block, creating a simple one-to-one replacement relationship that minimizes control complexity while improving reliability.
Solution Approach 2:
The redundant memory blocks serve multiple functions: they can replace any deteriorated regular memory block and maintain the same operational characteristics. This universality simplifies the replacement mechanism compared to specialized error correction circuits.
Data Source
AI summary
A memory device including a memory cell array, a redundant fuse circuit and a memory controller is provided. The memory cell array includes multiple regular memory blocks and multiple redundant memory blocks. The redundant fuse circuit includes multiple fuse groups recording multiple repair information. Each repair information is associated with a corresponding one of the redundant memory blocks and includes a repair address, a first enable bit, and a second enable bit. The memory controller includes multiple determining circuits. Each of the multiple determining circuits generates a hit signal according to an operation address, the repair address, the first enable bit, and the second enable bit. When a target memory block is bad, and the determining circuit of the memory controller generates the hit signal, the memory controller disables the redundant memory block that is bad according to the hit signal.