Tier-Based Sensing for Non-Volatile Memory Programming
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Solution Overview
Problem
In non-volatile memory systems, particularly in SLC-type programming operations, there is a need to improve programming speed while avoiding undesirable current fluctuations that could harm the memory structure or increase power consumption beyond safety thresholds, especially in applications with high program/erase cycles.
Innovation Solution
Implementing a tier-based sensing scheme where only a partial segment of memory cells is selected for bit scan mode during the program verify operation, applying a sensing bias voltage to specific bit lines, and initiating a bit scan mode for those selected cells, which reduces programming time without excessive current peaks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all memory cells are selected for bit scan mode during program verify operation, then programming speed is improved, but peak current consumption increases beyond safety thresholds
Solution Approach 1:
The memory block is divided into multiple segments, and only a subset of segments is selected for bit scan mode during program verify operations. This segmentation allows the system to achieve fast programming where needed while limiting current consumption by not activating all segments simultaneously, directly resolving the contradiction between programming speed and peak current usage.
Solution Approach 2:
Instead of applying bit scan mode to all memory cells (excessive action), the invention applies it only to a partial segment of memory cells during program verify operations. This partial action is sufficient to maintain acceptable programming speed while preventing peak current from exceeding safety thresholds, thus resolving the contradiction.
2Reliability
If all memory cells are sensed during program verify operation, then programming verification is thorough, but average current consumption increases
Solution Approach 1:
The sensing operation is segmented such that only specific bit lines corresponding to selected segments are activated during program verify. This selective sensing maintains verification reliability for the programmed data while reducing average current consumption by leaving other bit lines in a low-power state.
Solution Approach 2:
Different quality levels of sensing are applied to different parts of the memory block. Selected segments receive full sensing attention with bit scan mode activated, while other segments operate in a lower-power state. This local differentiation maintains overall verification reliability while reducing total current consumption.
3Measurement precision
If sensing bias voltage is applied to all bit lines, then all memory cells can be verified, but power consumption exceeds safe operating levels
Solution Approach 1:
The bit lines are divided into groups, and sensing bias voltage is applied only to the bit lines associated with selected segments during program verify operations. This selective voltage application maintains measurement precision for the programmed data while keeping power consumption within safe operating levels by excluding other bit lines from the high-voltage state.
Data Source
AI summary
A method for programming a memory block of a non-volatile memory structure, wherein the method provides, during a program verify operation, selecting only a partial segment of memory cells of a memory block for bit scan mode, applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells, and initiating a bit scan mode of the selected memory cells.