Multi-Level Memory Cell Programming Pulse Optimization
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Solution Overview
Problem
Multi-level memory cells face challenges in reliably distinguishing intermediate and erase cell states after numerous program/erase cycles or long data retention, leading to potential errors in read operations due to noisy distributions and increased latency.
Innovation Solution
A method that tracks the number of program/erase cycles and adjusts the programming voltage pulses to increase or narrow the target threshold voltage of the least significant bit, reducing the probability of erroneous reads by modifying the incremental step programming pulses, especially for cells with cold data or in archive storage scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard programming pulses are used, then write throughput is maintained, but the probability of erroneous reads increases after many program/erase cycles
Solution Approach 1:
The patent implements dynamic adjustment of programming pulse parameters based on the number of program/erase cycles. The system transitions from standard programming pulses to modified pulses with increased width or amplitude when cycle counters indicate degradation risk, allowing the programming mechanism to adapt its characteristics to maintain reliability while minimizing throughput impact
Solution Approach 2:
The patent changes physical parameters of the programming pulses (width, amplitude, duration) based on programmed cycle counts. By modifying these electrical parameters, the system shifts the threshold voltage distribution to prevent overlap between intermediate and erase states, thereby maintaining read accuracy without permanently sacrificing write throughput
2Reliability
If more program voltage pulses are applied, then the target threshold voltage increases and read accuracy improves, but programming time increases
Solution Approach 1:
The patent applies preliminary programming pulses before the cell reaches a critical degradation state. By proactively adjusting pulse parameters based on cycle counters, the system prevents threshold voltage distribution overlap before it occurs, avoiding the need for extensive re-programming or read correction later
Solution Approach 2:
The system implements periodic monitoring of program/erase cycle counts and applies adjusted programming pulses at predetermined intervals. This periodic intervention maintains threshold voltage separation without requiring continuous optimization, balancing reliability improvement with acceptable programming time increases
3Measurement precision
If narrower program voltage pulses are used, then the intermediate state precision improves and noise distribution tail reduces, but the programming process becomes more complex
Solution Approach 1:
The patent modifies the width parameter of programming pulses to create narrower pulses that produce more precise intermediate threshold voltage states. This parameter change reduces the noise distribution tail and minimizes overlap with erase states, improving measurement precision without fundamentally changing the programming architecture
Solution Approach 2:
The system uses feedback from cycle counters and read operations to adjust pulse width dynamically. By monitoring program/erase cycle counts and read accuracy, the system adapts pulse width parameters to maintain optimal intermediate state precision while managing the complexity through rule-based adjustments rather than complex control algorithms
Data Source
AI summary
In a data storage system having multi-level memory cells, a counter tracks the number of program/erase cycles, anticipated read cycles, or anticipated length of data retention of a cell. When a threshold number of cycles is reached or length of retention or read frequency are anticipated, the cell is programmed using more program voltage pulses, narrower program voltage pulses or some other modification to the incremental step programming pulse to reduce the range where the intermediate least significant (lower) bit read voltage may be erroneous, thereby reducing the probability of write errors when the most significant page (upper) is programmed.