Memory Cell Driver Circuit Voltage Range Control
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Solution Overview
Problem
Existing memory cell driver circuits face challenges in supplying accurate reference voltages for reading operations due to the limited voltage driving capacity of NMOS transistors, which results in failure to reach the targeted supply voltage level, leading to inaccurate verification of memory cell states.
Innovation Solution
A driver circuit comprising stacked PMOS and NMOS transistors in series, with a third control circuit managing gate control signals to provide a wider range of read reference voltages, enabling accurate voltage supply to memory cells during read operations by activating specific transistors for charging and discharging paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If NMOS transistors are used to supply reference voltage for reading memory cells, then the circuit complexity is reduced, but the voltage driving capacity is insufficient to reach the targeted supply voltage level
Solution Approach 1:
The reference voltage supply circuit is segmented into multiple independent voltage generation paths: a first circuit using NMOS transistors for low voltage operation (0V to VDD-Vth), and a second circuit using PMOS transistors for high voltage operation (VDD-Vth to VDD). This segmentation allows each circuit to be optimized for its specific voltage range, resolving the contradiction between simplicity and voltage capacity.
Solution Approach 2:
The system dynamically switches between different voltage supply circuits based on operational requirements. A control circuit selectively activates the first circuit for low voltage reading operations and the second circuit for high voltage programming/erasing operations, enabling the memory device to adapt its voltage driving capacity to the specific operation being performed.
2Device complexity
If a single voltage supply circuit is used, then the device complexity is reduced, but the adaptability to different voltage requirements is limited
Solution Approach 1:
The memory device incorporates multiple voltage supply circuits that can serve different functions: the first circuit handles low voltage reading operations, while the second circuit handles high voltage programming and erasing operations. This multi-functionality allows a single memory device to perform diverse operations with different voltage requirements without requiring external voltage sources.
Solution Approach 2:
The control circuit dynamically selects which voltage supply circuit to activate based on the operation being performed. This dynamic adaptability enables the system to switch between voltage ranges (low voltage for reading, high voltage for programming/erasing) as needed, providing versatility while maintaining a relatively simple overall circuit architecture.
3Ease of manufacture
If NMOS transistors are used for voltage supply, then the manufacturing process is simplified, but the measurement precision of memory cell states is degraded
Solution Approach 1:
The voltage supply functionality is segmented into two circuits: the first circuit using NMOS transistors for low voltage reading operations where manufacturing simplicity is advantageous, and the second circuit using PMOS transistors for high voltage programming/erasing operations where achieving the targeted voltage level is critical for accurate state verification.
Solution Approach 2:
The system changes the voltage parameter supplied to the memory cell based on the operation being performed. Low voltage (0V to VDD-Vth) is used for reading operations where NMOS transistors provide sufficient precision, while high voltage (VDD-Vth to VDD) is used for programming and erasing operations where the second circuit ensures accurate state verification.
Data Source
AI summary
A driver circuit for operating a memory cell, adapted to be coupled to at least one memory cell through a respective output node, said driver circuit including: a first circuit for supplying the memory cell with a first read reference voltage through the output node; a second circuit for supplying the memory cell with a second read reference voltage through the output node; and a third circuit for controlling an operation of the second circuit, wherein a range of the second read reference voltage at the output node is wider than a range of the first read reference voltage at the output node during a read operation on the memory cell.