Programmable Memory Cell Anti-Fuse Structure Area Optimization

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Solution Overview

Problem

Existing one-time programmable storage cells have complex structures, occupy large areas, and exhibit slow data reading speeds and poor reliability due to their intricate structures and parasitic capacitance and resistance issues in dynamic random access memory applications.

Innovation Solution

A programmable storage cell design featuring anti-fuse elements and switch units connected to power terminals and position signal terminals, allowing for simplified structure and reduced area usage by eliminating the need for sensitivity amplifiers and combining position signal terminals through an AND gate, with distinct voltage levels for writing and reading operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If existing one-time programmable storage cell structures are used, then storage functionality is achieved, but structure complexity increases and area occupation increases

Engineering Contradiction:

Improvestorage cell structureVSAvoidstorage reliability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The storage cell is segmented into distinct functional blocks: word line decoding circuit, bit line decoding circuit, anti-fuse array, and sense amplifier. Each segment performs a specific function, allowing independent optimization and reducing overall complexity while maintaining reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Decoding circuits are introduced as intermediary components between control signals and the anti-fuse array. These intermediaries translate control signals into appropriate activation patterns, simplifying the control logic while ensuring reliable operation of the storage cell.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Area of stationary object

If existing one-time programmable storage cell structures are used, then storage functionality is achieved, but area occupation increases

Engineering Contradiction:

Improvestorage cell areaVSAvoiddata reading speed

Core Design Contradiction:

Area of stationary objectVSSpeed

Solution Approach 1:

Multiple decoding functions are merged into compact decoding circuits that share common control signals and transistors. The word line and bit line decoding circuits are integrated closely with the anti-fuse array, reducing the total area while maintaining fast read access through optimized signal paths.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The storage cell layout transitions from planar expansion to multi-layer integration. Anti-fuses are arranged in a two-dimensional array with vertical connections through multiple metal layers, allowing high-density packing that reduces area occupation while maintaining fast read speeds through short interconnect paths.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Speed

If existing one-time programmable storage cell structures are used, then storage functionality is achieved, but data reading speed decreases

Engineering Contradiction:

Improvedata reading speedVSAvoidstorage cell structure

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The sense amplifier is extracted as a dedicated component separate from the anti-fuse array, specifically optimized for fast read operations. This extraction allows the sense amplifier to be minimized in area while providing high-speed read capability, without adding unnecessary complexity to the programming path.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

Word lines and bit lines are pre-charged to specific voltage levels before read operations. The decoding circuits prepare the appropriate lines in advance, reducing the actual read time. This preliminary action enables fast read speeds while keeping the overall structure relatively simple.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design simplifies the structure, reduces area occupation, enhances reading speed, and improves stability by providing a large differential voltage during data read operations, thus addressing the limitations of existing one-time programmable storage cells.

Implementation Method 1

applying a breakdown voltage between a first power terminal and a second power terminal to break down the at least one anti-fuse

Methodology Applied

Scientific EffectAvalanche breakdown: Avalanche Breakdown

Data Source

PatentUS11735279B2Programmable memory cell, memory array and reading and writing method thereof

Publication Date: 2023.08.22 CHANGXIN MEMORY TECH INC

AI summary

The present disclosure in the field of memory technology proposes a programmable storage cell, a programmable storage array and a reading and writing method for the programmable storage array. The programmable storage cell includes: a first anti-fuse element connected between a first power terminal and an output terminal, a second anti-fuse element connected between the second power terminal and the output terminal, and a third switch unit connected to the output terminal, a third power terminal and a position signal terminal, where the third switch unit responds to the signal from the position signal terminal so as to connect the third power terminal and the output terminal. The programmable storage cell has a simple structure and a high reading speed.