Memory Controller Write Pulse Adjustment for Imprint Mitigation
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Solution Overview
Problem
Memory devices face challenges in maintaining data integrity due to non-uniform electrical characteristics of memory cells, which can lead to errors in read operations and degradation of reset margins, particularly due to the imprint effect caused by repeated read operations.
Innovation Solution
A dynamic approach is implemented where a memory device controller determines whether to enhance a write pulse based on a lookup table associated with prior read operations. The controller selectively uses either a regular or an enhanced write pulse, increasing the write voltage or current as needed, to mitigate the imprint effect and maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If repeated read operations are performed on memory cells, then data access is enabled, but imprint effect occurs causing degradation of reset margins and write endurance
Solution Approach 1:
The system performs preliminary read operations to detect the imprint effect on memory cells before write operations occur. By identifying cells that have undergone repeated reads and exhibit imprint effects, the system can proactively adjust write pulse strengths to compensate for the degradation, thereby maintaining write endurance and reset margins.
Solution Approach 2:
The system dynamically changes the write pulse parameter (strength/intensity) based on the detected read history of memory cells. Cells that have experienced repeated reads and show imprint effects receive enhanced write pulses, while cells without imprint effects receive normal write pulses. This parameter adaptation resolves the contradiction by maintaining write reliability without unnecessarily increasing write strength for all cells.
2Reliability
If stronger write pulses are applied to all memory cells, then write reliability is improved, but write endurance and energy consumption worsen
Solution Approach 1:
The system applies different write pulse strengths to different memory cells based on their individual read histories and imprint effect characteristics. Only memory cells that have experienced repeated reads and exhibit imprint effects receive stronger write pulses, while other cells receive normal write pulses. This localized approach ensures write reliability for affected cells without unnecessarily consuming energy on cells that do not require enhanced writing.
Solution Approach 2:
The system applies excessive (stronger) write pulses only partially, specifically to memory cells that have undergone repeated read operations and exhibit imprint effects. This partial application of excessive action ensures that write reliability is maintained for the affected subset of cells while avoiding the energy consumption penalty of applying strong write pulses to all cells in the array.
3Reliability
If write pulse strength is increased to compensate for imprint effect, then reset margin degradation is reduced, but energy consumption increases
Solution Approach 1:
The system dynamically changes the write pulse parameter (strength) based on the detected imprint effect in memory cells. By monitoring read operations and identifying cells with degraded reset margins, the system adjusts the write pulse strength only for those specific cells, thereby maintaining reset margin reliability without the energy loss associated with uniformly increasing write pulse strength across the entire memory array.
Data Source
AI summary
Systems, methods, and apparatus to select an enhanced write pulse for a write operation in a memory device. In one approach, stronger reset pulses are triggered when there is an increased risk of memory cell threshold voltage degradation. Memory cells read by a relatively higher number of read operations are recorded by a controller of a memory device by updating a lookup table with addresses of the memory cells read. For a new write operation, the controller determines if a reset on set write operation is to be performed. The controller also searches the lookup table to determine if an address for the target bits or codeword of the write operation are in the lookup table. If both conditions are satisfied, then the magnitude of the write pulse is increased for programming the memory cells.