BIST Module Autonomous Address Generation for Memory Testing
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Solution Overview
Problem
Highly integrated semiconductor devices face challenges in efficient testing due to lower memory yield and increased complexity, with existing methods like BIST requiring significant resources and dependence on external commands for testing.
Innovation Solution
A memory test apparatus and method that includes a BIST module connected to automatic test equipment, capable of autonomously generating addresses and executing test procedures using FSM operation commands, and performing auto-operation tests on specified regions when receiving direct access commands, reducing dependence on external equipment and improving test efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If traditional BIST methods are used for testing embedded memories, then testing can be performed within the device, but resource consumption increases and debugging capability is limited
Solution Approach 1:
The memory device performs self-testing through autonomous address generation and test execution. The BIST module generates test addresses and commands independently, allowing the device to test itself without extensive external equipment, thereby reducing resource consumption while maintaining automation.
Solution Approach 2:
A test interface circuit is introduced as an intermediary between the external test environment and the memory device. This interface simplifies the connection requirements and enables autonomous testing by mediating the interaction between external commands and internal BIST operations.
2Adaptability or versatility
If highly integrated memory devices are used to increase functionality, then device capabilities improve, but memory yield decreases and testing becomes more difficult
Solution Approach 1:
The memory device is divided into multiple banks, allowing independent testing of each bank. This segmentation enables targeted testing of specific memory regions, improving test efficiency and yield by isolating defects to specific segments rather than requiring complete device rework.
Solution Approach 2:
The BIST module dynamically changes test parameters such as address generation patterns and test commands to adapt to different memory configurations and defect types, enabling effective testing across highly integrated devices with varying functionalities.
3Measurement precision
If comprehensive testing of entire memory regions is performed, then defect detection capability improves, but testing time increases
Solution Approach 1:
The system performs partial testing by allowing selective testing of specific memory banks or regions based on received address information. When a direct access command is received, only the specified test region is tested rather than the entire memory device, reducing testing time while maintaining defect detection capability for critical regions.
Solution Approach 2:
The testing approach dynamically adapts based on the received command type. The BIST module can switch between comprehensive testing modes and targeted testing modes, adjusting the scope of testing to balance defect detection accuracy with testing time requirements.
4Extent of automation
If autonomous address generation is implemented in BIST module, then dependence on external equipment reduces, but control flexibility over test regions decreases
Solution Approach 1:
The BIST module is designed with multi-functionality to handle both autonomous address generation and external address input. It can operate in two modes: generating addresses autonomously for comprehensive testing, or accepting external address information for targeted testing of specific regions, thereby maintaining both automation and flexibility.
Solution Approach 2:
The address generation mechanism dynamically switches between autonomous generation and external input based on the command received. This dynamic capability allows the system to adapt to different testing scenarios, maintaining both high automation and test region flexibility.
Data Source
AI summary
A method of testing using a memory test apparatus connected to a memory device includes receiving a test command. When the test command is a finite state machine (FSM) operation command, the memory device is tested in accordance with the FSM operation command, and an operation is performed to output a result depending on a pass/fail result. But, when the test command is a direct access command, an auto-operation test of input data is performed in a test region according to received address information, and a test result is output, which may include output data with fail information or the auto-operation.