Nonvolatile Memory Wear Leveling via Fail Bit Count Management
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Solution Overview
Problem
In memory devices, wear leveling is challenging due to variations in block characteristics, leading to uneven erase counts and fail bit counts, which can result in the formation of bad blocks and reduced memory capacity.
Innovation Solution
A controller manages both erase counts and fail bit counts for each block, selecting a write target block based on these metrics to ensure even wear distribution and prevent bad block formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If erase operation is executed equally at all blocks to control wear leveling, then wear distribution is improved, but fail bit count increases leading to bad block formation
Solution Approach 1:
The patent applies local quality by differentiating block management based on individual block characteristics. Blocks are classified into different groups (first group with lower fail bit count, second group with higher fail bit count) and subjected to different erase operations. This allows wear leveling to be applied selectively - more aggressive erasing to blocks that can tolerate it while protecting vulnerable blocks, thereby resolving the contradiction between uniform wear distribution and preventing bad block formation.
2Productivity
If erase operation frequency increases to maintain wear leveling, then wear control is improved, but fail bit count increases reducing memory capacity
Solution Approach 1:
The patent changes the parameter of erase operation frequency based on block characteristics. By monitoring fail bit counts and adjusting erase frequency accordingly, the system optimizes the balance between wear leveling productivity and memory capacity preservation. Blocks in the first group undergo more frequent erasing while blocks in the second group undergo less frequent erasing, maximizing overall system productivity while preserving usable memory capacity.
Data Source
AI summary
According to one embodiment, a memory device includes a controller, and a nonvolatile memory in which an erase operation is controlled by the controller, the nonvolatile memory including blocks, the erase operation executing every block, the nonvolatile memory transferring a first reply showing a completion of the erase operation and a fail bit count showing a number of memory cells in which a data erase is uncompleted after the completion of the erase operation to the controller. The controller selects a target block as a target of the erase operation based on the fail bit count.