Non-Volatile Memory Erase Method Using GIDL Transistors
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Solution Overview
Problem
Existing non-volatile memory devices face challenges in reducing the occurrence of deep erase cells, which can lead to reliability issues and inefficiencies in memory operations.
Innovation Solution
The implementation of a non-volatile memory device with a memory cell array comprising gate-induced drain leakage (GIDL) transistors and a control logic that performs specific erase, verification, and programming operations, including applying voltages to bit lines and GIDL lines to manage electron and hole levels in memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional erase operations are performed on non-volatile memory devices, then memory cells are erased, but deep erase cells occur leading to reliability issues
Solution Approach 1:
The patent applies preliminary action by performing a first erase operation followed by a verification operation before performing additional erase operations. This preliminary verification step identifies cells that require further erasure, allowing the system to target only those specific cells with subsequent erase operations rather than uniformly erasing all cells multiple times, thereby preventing deep erase conditions
Solution Approach 2:
The patent implements feedback through the verification operation that detects erase results after each erase operation. This feedback mechanism provides information about which memory cells have been successfully erased and which require further erasure, enabling the control logic to adjust subsequent erase operations accordingly and avoid over-erasing cells that are already erased
2Manufacturing precision
If multiple erase operations are performed to ensure complete erasure, then erase completeness improves, but occurrence of deep erase cells increases
Solution Approach 1:
The patent performs a preliminary erase operation followed by verification to identify which cells actually need further erasure. This preliminary step ensures that subsequent erase operations are targeted only at cells that require them, achieving complete erasure without subjecting already-erased cells to additional erase cycles that would create deep erase conditions
Solution Approach 2:
The patent applies partial action by performing erase operations selectively based on verification results. Instead of applying excessive erase operations uniformly to all cells, the system applies additional erase operations only to the specific subset of cells that verification identifies as requiring further erasure, thus achieving complete erasure while avoiding deep erase of cells that are already sufficiently erased
3Productivity
If GIDL transistors are programmed at higher levels to improve erase capability, then erase effectiveness improves, but control precision decreases
Solution Approach 1:
The patent segments the erase process into multiple distinct operations: a first erase operation, verification operation, and conditional second erase operation. This segmentation allows the system to use different GIDL transistor programming levels for different stages, achieving both high erase effectiveness in critical stages and precise control in verification and conditional stages
Solution Approach 2:
The patent applies dynamics by making the GIDL transistor programming level adaptive rather than fixed. The control logic dynamically adjusts whether to perform additional erase operations based on verification results, and can program GIDL transistors at different levels (first level or second level) depending on the specific erase requirements, thus balancing effectiveness and precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses the occurrence of deep erase cells, enhancing the reliability and efficiency of memory operations by finely controlling erase processes and maintaining optimal electron and hole levels.
Implementation Method 1
each of the plurality of cell strings includes a gate-induced drain leakage (GIDL) transistor
Data Source
AI summary
A non-volatile memory device includes a memory cell array including a plurality of cell strings, each of the plurality of cell strings includes a gate-induced drain leakage (GIDL) transistor and a memory cell group, and a control logic to apply a voltage to each of the plurality of cell strings. The control logic performs a first erase operation of erasing the memory cell groups of each of the plurality of cell strings, a first verification operation of detecting erase results of the memory cell groups of each of the plurality of cell strings, and a program operation of programming the GIDL transistors of some of the plurality of cell strings.