Nonvolatile Memory Cell Sidewall Charge Trapping
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Solution Overview
Problem
The miniaturization of semiconductor devices makes it difficult to align impurity diffusion regions with sidewalls in nonvolatile memory cells, leading to inadequate depletion layers and insufficient hot carrier injection into the sidewall charge trapping layer, which affects the retention of data in the absence of a power supply.
Innovation Solution
A nonvolatile memory cell configuration that includes a silicon substrate, a metal layer, a conductivity-type diffusion layer, an insulating film, a gate electrode, and sidewalls made of insulating material, where the metal layer and diffusion layer are separated by the substrate, and the sidewalls are designed to enhance charge trapping by forming a potential well, allowing precise alignment through silicidation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the device is miniaturized, then the device size is reduced, but the alignment precision between impurity diffusion regions and sidewalls deteriorates
Solution Approach 1:
The patent forms the sidewall structure before forming the impurity diffusion region, establishing a reference structure in advance. The sidewall is created as an insulating layer patterned and deposited on the substrate, then the impurity diffusion region is formed using the sidewall as a mask or alignment reference, ensuring proper spatial relationship despite miniaturization
2Ease of manufacture
If the impurity diffusion region is formed using gate electrode and sidewalls as mask, then the manufacturing process is simplified, but the depletion layer formation under sidewall becomes insufficient
Solution Approach 1:
The patent creates a localized depletion layer directly under the sidewall by controlling the impurity concentration and type in that specific region. The sidewall region is engineered to have different electrical characteristics than other areas, ensuring that when bias is applied, a strong depletion layer forms locally under the sidewall to enable effective hot carrier injection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures the presence of a depletion layer under the sidewall, enabling effective hot carrier injection and data retention, even in the absence of power, by maintaining the strength of the electric field and enhancing charge trapping capabilities.
Implementation Method 1
The hot-carrier effect refers to the injection of electrons into the gate insulating film and/or sidewall of a MIS transistor
Implementation Method 2
the strongest electric field in the horizontal direction occurs in this depletion layer in the proximity of the drain. Some of the electrons accelerated by this strong electric field and thus having high energy are injected into the gate insulating film and/or sidewall
Implementation Method 3
the gate insulating film and/or sidewall serve as a charge trapping layer. For the purpose of keeping the injected electrons trapped in the charge trapping layer
Data Source
AI summary
A nonvolatile memory cell includes a first-conductivity-type silicon substrate, a metal layer formed in a surface of the first-conductivity-type silicon substrate, a second-conductivity-type diffusion layer formed in the surface of the first-conductivity-type silicon substrate and spaced apart from the metal layer, an insulating film disposed on the surface of the first-conductivity-type silicon substrate between the metal layer and the second-conductivity-type diffusion layer, a gate electrode disposed on the insulating film between the metal layer and the second-conductivity-type diffusion layer, and a sidewall disposed at a same side of the gate electrode as the metal layer and situated between the gate electrode and the metal layer, the sidewall being made of insulating material.