Multi-level Memory Cell Using Electron Discharge Time Measurement
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Solution Overview
Problem
Current semiconductor memory cells face limitations in storing multiple bits due to the limited spectrum width of physical parameters, which affects the accuracy of programming and reading characteristic values, especially as the number of levels increases, and is prone to interference from electrical noise and sense voltage disturbances.
Innovation Solution
A memory cell system that utilizes electron discharge times as a characteristic parameter, where the effective resistance of the memory cell affects the discharge time, allowing for multi-bit binary value representation by associating different target discharge times with binary values, and using statistical methods to determine the closest match during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of levels in a memory cell increases to store more bits, then the storage capacity increases, but the measurement precision of the characteristic parameter deteriorates due to spectrum width limitations and electrical noise interference
Solution Approach 1:
The patent changes the measured parameter from the characteristic parameter itself (e.g., resistance, capacitance) to the time delay of a signal passing through the memory cell. This time delay parameter is affected by the characteristic parameter but provides better measurement precision because it can be measured with higher accuracy using timing circuits, thus resolving the contradiction between storage capacity and measurement precision
Solution Approach 2:
The patent introduces an intermediary measurement approach where instead of directly measuring the characteristic parameter, a signal is passed through the memory cell and the time delay of this signal is measured. This intermediary time delay measurement serves as a more precise proxy for the characteristic parameter value, enabling accurate reading even with multiple storage levels
2Quantity of substance
If the number of levels in a memory cell increases to store more bits, then the storage capacity increases, but the reliability of data retrieval deteriorates due to electrical noise and sense voltage disturbance
Solution Approach 1:
By changing from direct characteristic parameter measurement to time delay measurement, the system achieves better noise immunity. Time delay measurements are less susceptible to electrical noise and voltage disturbances compared to direct resistance or capacitance measurements, thus improving reliability while maintaining multi-level storage capability
Solution Approach 2:
The patent replaces the electrical measurement system (direct voltage/current measurement of characteristic parameters) with a timing-based measurement system. This substitution uses signal propagation time through the cell, which provides inherent noise rejection and improves reliability in the presence of electrical disturbances
3Device complexity
If direct characteristic parameter measurement is used, then the device complexity is low, but the measurement precision deteriorates due to spectrum width limitations
Solution Approach 1:
The patent introduces an intermediary signal transmission process where a known signal is applied to the memory cell and the output signal's time delay is measured. This adds some circuit complexity (signal source, timing measurement circuit) but dramatically improves measurement precision by converting the measurement into a time-based operation that is less affected by spectrum width limitations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate and efficient storage and retrieval of multiple bits in a single memory cell by minimizing perturbation during read/write processes, improving the spectrum of physical parameter variations and reducing errors caused by noise and disturbances.
Implementation Method 1
the time required for voltage to be discharged through an electronic circuit formed, at least partially, by the memory cell
Implementation Method 2
an intrinsic resistor-capacitor circuit
Data Source
AI summary
A computer program product for operating a memory cell and memory array. The computer program product of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.