Delayed Dummy Word Line Ramp-Up Reduces Channel Gradient Disturbs
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Solution Overview
Problem
In memory devices, particularly in 3D NAND structures, disturbs in the threshold voltage (Vth) of select gate transistors and dummy memory cells can occur due to channel gradients during programming operations, leading to increased Vth levels over time, which can affect the reliability and efficiency of program, erase, and read operations.
Innovation Solution
Implementing a delayed ramp-up of the dummy word line voltage relative to the data word lines during the program phase, and using additional dummy memory cells to shift disturbs from drain-side data memory cells, while adjusting the strength of disturb countermeasures based on the position of the selected data memory cell within the memory string.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dummy word line voltage is ramped up concurrently with data word lines during programming, then programming speed is maintained, but channel gradients increase causing disturb in select gate transistors and dummy memory cells
Solution Approach 1:
The dummy word line voltage ramp-up is delayed until after the data word line voltage has been applied, creating a preliminary action sequence that prevents channel gradient formation. This timing separation ensures that the dummy memory cells are not disturbed during the critical programming phase while maintaining programming speed.
Solution Approach 2:
The patent implements dynamic control of the dummy word line voltage timing, adjusting the ramp-up sequence based on the programming phase. During programming, the dummy word line voltage is delayed, while during verification it can be applied concurrently, allowing the system to adapt to different operational requirements and minimize disturbs only when necessary.
2Reliability
If additional dummy memory cells are added to shift disturbs, then reliability of data memory cells improves, but device complexity increases
Solution Approach 1:
Additional dummy memory cells are introduced as intermediary elements between the select gate transistors and the data memory cells. These dummy cells act as buffers that absorb and redirect channel gradients away from the data memory cells, preventing disturbs while maintaining the overall memory string structure and functionality.
Solution Approach 2:
The patent applies different functional qualities to different regions of the memory string. Dummy memory cells are strategically placed at specific locations (e.g., near select gate transistors) where they serve as disturbance sinks, while data memory cells in other regions maintain their primary storage function. This localized differentiation protects critical data cells without requiring universal structural changes.
Data Source
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AI summary
A memory device and associated techniques for reducing disturbs of select gate transistors and dummy memory cells in a memory device. In one approach, a ramp up of the voltage of a dummy word line is delayed relative to a ramp up of a voltage of data word lines in a program phase of a program loop, after a pre-charge phase of the program loop. Another possible approach delays the ramp up of a first dummy memory cell while the voltage of a second dummy memory cell is maintained at an elevated level throughout the pre-charge phase and the program phase. In another aspect, the disturb countermeasure is used when the selected data memory cell is relatively close to the source-end of the memory string and phased out when the selected data memory cell is relatively close to the drain-end of the memory string.