Semiconductor Memory Device With Segmented MLC SLC Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multilevel NAND flash memories face slower write speeds due to the need for narrower threshold voltage distributions when storing multiple bits of data per cell, which increases write time and reduces capacity compared to single-level NAND flash memories.
Innovation Solution
A semiconductor memory device with a memory cell array comprising both multilevel (MLC) and single-level (SLC) regions, where data is decentralized across these regions using a control circuit to distribute write operations, allowing for efficient storage and retrieval of n-bit and k-bit data by utilizing multiple data caches and a control circuit to manage data between the regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multilevel NAND flash memory stores multiple bits of data in a single memory cell, then storage capacity increases, but write time increases and write speed decreases
Solution Approach 1:
The memory cell array is divided into multiple regions (first region with n-bit memory cells and second region with k-bit memory cells where k>n). This segmentation allows the system to distribute data storage across different memory cell types, enabling parallel write operations to occur simultaneously in both regions, thereby increasing overall write speed while maintaining high storage capacity through the k-bit memory cells.
2Quantity of substance
If the distribution width of threshold voltage is narrowed to store more bits per memory cell, then storage capacity increases, but write speed decreases
Solution Approach 1:
The memory system segments memory cells into different types with different threshold voltage distribution characteristics. The first region uses memory cells with narrower threshold voltage distribution for storing k-bit data, while the second region uses memory cells with wider distribution for n-bit data. This allows parallel writes to proceed simultaneously without the bottleneck of narrow distribution control, maintaining high write speed while achieving high capacity through the k-bit cells.
Solution Approach 2:
Instead of increasing bits per cell in a single dimension by narrowing threshold voltage distribution, the invention adds a spatial dimension by creating multiple memory regions with different characteristics. This dimensional approach allows simultaneous access and write operations across regions, bypassing the speed penalty associated with narrow threshold voltage distribution while still achieving high storage capacity.
3Speed
If single-level NAND flash memory is used, then write speed increases, but storage capacity decreases
Solution Approach 1:
The memory cell array is segmented into a first region with n-bit memory cells optimized for fast write operations and a second region with k-bit memory cells (k>n) optimized for high capacity. The control circuit distributes write operations to both regions simultaneously, allowing the system to achieve write speeds comparable to single-level memory through the first region while attaining high storage capacity through the second region.
Solution Approach 2:
The invention transitions from a single-dimension approach (choosing between speed or capacity) to a two-dimension approach by creating multiple memory regions with different characteristics. This allows the system to operate in both speed-optimized and capacity-optimized modes simultaneously through parallel writes, achieving both high write speed and high storage capacity.
Data Source
AI summary
A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing k-bit data (k>n: k is a natural number), a data storage circuit which includes a plurality of data caches, and a control circuit which controls the memory cell array and the data storage circuit in such a manner that the k-bit data read from the k/n number of memory cells in the first region are stored into the data storage circuit and the k-bit data are stored into the memory cells in the second region.