MLC NAND Programming via Bit Line Voltage Swing Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multi-state programming operations in non-volatile memory systems, such as MLC and TLC, face challenges with slower programming speeds and increased power consumption due to the need to precisely control multiple threshold voltage ranges, which tightens tolerances and increases energy demands.
Innovation Solution
A method involving a series of program pulses with specific voltages and conditions, including inhibit and zero voltage conditions applied to bit lines, to program multiple states efficiently, reducing the voltage swing experienced by adjacent bit lines and optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-state programming operations are performed to increase storage density, then storage capacity per cell is improved, but programming speed deteriorates and power consumption increases
Solution Approach 1:
The programming operation is divided into multiple sequential program pulses (first program pulse, second program pulse, third program pulse), each targeting a specific voltage range. This segmentation allows precise control of threshold voltage steps while managing power consumption and maintaining programming speed through structured progression.
Solution Approach 2:
The patent employs periodic voltage conditions including inhibit conditions and zero voltage conditions applied to bit lines during each program pulse. This periodic action pattern reduces voltage swings on adjacent bit lines and optimizes power consumption while maintaining programming efficiency across multiple states.
2Quantity of substance
If multiple threshold voltage ranges are targeted to store multiple bits per cell, then storage density is improved, but power consumption increases
Solution Approach 1:
The patent systematically changes voltage parameters across multiple program pulses, with each pulse applying a specific programming voltage to achieve distinct threshold voltage ranges. This parameter progression enables multi-bit storage while controlling power consumption through optimized voltage sequencing and inhibit conditions on bit lines.
Solution Approach 2:
By applying inhibit conditions and zero voltage conditions periodically during each program pulse, the patent reduces unnecessary voltage swings on adjacent bit lines. This periodic control minimizes energy consumption while maintaining the ability to program multiple threshold voltage states for increased storage density.
3Measurement precision
If tight voltage tolerances are applied to achieve precise multi-state programming, then programming accuracy is improved, but power consumption and operational complexity increase
Solution Approach 1:
The programming operation is segmented into multiple discrete program pulses, each targeting a specific voltage range with controlled precision. This segmentation enables tight voltage tolerances to be achieved step-by-step rather than in a single operation, reducing the power consumption associated with high-precision multi-state programming.
Solution Approach 2:
The patent employs periodic inhibit conditions and zero voltage conditions during each program pulse to maintain precise voltage control. This periodic action reduces voltage swings on adjacent bit lines and minimizes power consumption while achieving the tight tolerances necessary for accurate multi-state programming.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances programming speed and reduces power consumption by balancing voltage biasing schemes, specifically during the second program pulse where power spikes occur, thereby improving the efficiency and longevity of memory devices.
Implementation Method 1
bit-value data can be programmed onto and erased from a memory cell by precisely changing the level of electron charges on a floating gate in order to change the threshold voltage (Vth) characteristic of the transistor
Implementation Method 2
a minimum amount of voltage that must be applied to the control gate before the transistor is activated to permit conduction between its source and its drain regions is, therefore, determined by the level of charge that is retained on the floating gate
Implementation Method 3
during each of the first program pulse, second program pulse, and third program pulse, applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array
Data Source
AI summary
A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array such that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.