Small Antifuse Voltage Generator for High-Density Memory
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Solution Overview
Problem
Conventional antifuse circuits are large in size, limiting their placement on memory chips and reducing design flexibility and performance due to the need for voltage circuits and antifuse circuits that are not optimized for location.
Innovation Solution
A memory system with a small-sized antifuse voltage generator of low hardware complexity, comprising a control block, antifuse voltage generator, and array voltage generator, allowing for optimal placement on the chip and enhanced design flexibility by using simple circuits for voltage boosting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional antifuse circuits are used, then voltage boosting capability is achieved, but circuit size becomes large
Solution Approach 1:
The antifuse voltage generator is divided into two independent sub-circuits: a first sub-circuit for generating high voltage during programming operations and a second sub-circuit for maintaining normal voltage during reading operations. This segmentation allows each sub-circuit to be optimized for its specific function, reducing the overall circuit size while maintaining voltage boosting capability when needed.
Solution Approach 2:
The circuit dynamically switches between two operational modes: during programming operations, the first sub-circuit activates to provide voltage boosting; during reading operations, the second sub-circuit operates to maintain normal voltage levels. This dynamic operation allows the circuit to achieve voltage boosting capability only when required, minimizing the active circuit area at any given time.
2Power
If large size voltage circuits are used for high density memory, then voltage boosting capability is maintained, but design flexibility and placement optimization are reduced
Solution Approach 1:
By segmenting the voltage generator into two smaller sub-circuits, the design achieves both voltage boosting capability and improved adaptability. The smaller circuit area allows for flexible placement on high-density memory chips, enabling optimal positioning to enhance performance while maintaining the necessary voltage boosting function.
Data Source
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AI summary
A memory system (100) includes a control block (10), an antifuse voltage generator (11), an array voltage generator (12), and a memory array (13). The control block (10) is used to output control signals (AS, BST, C3, C4) for controlling the memory array (13) according to a memory control data signal (MCDS). The antifuse voltage generator (11) is used for outputting an antifuse control signal (AF) to the memory array (13) according to a control signal (BST) and a driving voltage (VDDIN). The array voltage generator (12) is used for outputting a selection signal (SL) and a following control signal (FL) to the memory array (13) according a control signal (C3) . The memory array (13) is coupled to the control block (10), the antifuse voltage generator (11), and the array voltage generator (12) for accessing data according to a first control signal (AS), the antifuse control signal (AF), the selection signal (SL), and the following control signal (FL) . The first control signal (AS) includes address information of the memory array (13).