Memory Circuit Complementary Cell Erase-State Check
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Solution Overview
Problem
The existing memory circuit designs for semiconductor memory apparatuses are complex and require an external terminal for the erase-state check function, making the operation cumbersome and necessitating additional components.
Innovation Solution
The memory circuit incorporates a complementary cell configuration with a first and second memory cell, each connected to a selection transistor, and a reference cell, where the erase-state check is simplified by applying a power-supply voltage to the control gates of the memory transistors, eliminating the need for an external terminal by ensuring the threshold voltage in the erase state is secured to be higher than the power-supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an external terminal is used for erase-state check function, then the memory circuit can perform threshold voltage detection, but the device complexity increases and operation becomes cumbersome
Solution Approach 1:
The patent extracts the erase-state check function from the external terminal dependency and integrates it into the memory circuit itself. By using the power-supply voltage to directly apply to control gates of memory transistors and measuring drain currents through bit lines, the external terminal is eliminated while maintaining threshold voltage detection capability.
Solution Approach 2:
The power-supply voltage serves multiple functions: it provides operational power to the memory circuit and simultaneously enables the erase-state check function by being applied to control gates. This multi-functionality eliminates the need for separate external terminals for threshold voltage detection.
2Measurement precision
If an external terminal is used for erase-state check function, then threshold voltage can be measured, but additional components and operational steps are required
Solution Approach 1:
The memory circuit performs self-diagnosis through the erase-state check function. The power-supply voltage automatically applies to control gates when memory transistors are in erase state, enabling the circuit to self-measure threshold voltage without external intervention or complex operational sequences.
3Device complexity
If threshold voltage in erase state is secured to be higher than power-supply voltage, then external terminal is eliminated, but the memory transistor design becomes more constrained
Solution Approach 1:
The patent changes the threshold voltage parameter by ensuring it is higher than the power-supply voltage in the erase state. This parameter adjustment enables the memory transistor to block current flow during normal operation while allowing the power-supply voltage to effectively test the erase state, thereby simplifying the circuit design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration simplifies the erase-state check function, reduces the complexity of the memory circuit, and eliminates the need for an external terminal, enhancing operational efficiency and reducing component requirements.
Implementation Method 1
erasing and writing (programming) are performed by application of high voltage to an oxide film adjacent to the floating gate to cause electrons to be injected into and extracted from the floating gate
Implementation Method 2
a sense amplifier that measures a threshold voltage of the memory transistors in an erase state by measuring a drain current in response to a gate voltage
Data Source
AI summary
Provided is a memory circuit that is provided to an IC chip, the memory circuit including: a complementary cell which includes a first memory cell that includes a first memory transistor, and a second memory cell that includes a second memory transistor; a reference cell which includes a reference transistor; a first terminal which is connectable to a gate of the first memory transistor and a gate of the second memory transistor, and to which a first power-supply voltage can be applied; a second terminal which is connectable to a gate of the reference transistor, and to which a second power-supply voltage can be applied; and a detection unit which detects a magnitude relationship between current that flows through the first memory cell or the second memory cell, and current that flows through the reference cell.