3D NAND Contact Formation via Segmented Conductive Layers
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Solution Overview
Problem
In three-dimensional nonvolatile memory devices, the ends of conductive layers are stepped, and contacts are disposed to prevent short-circuiting with lower conductive layers, but existing methods face challenges in accurately connecting contacts without penetrating the upper conductive layers, leading to potential short circuits or open defects due to trade-offs in etching conditions.
Innovation Solution
A semiconductor storage device design featuring a stacked body with alternately layered conductive and insulating layers, including a stepped portion with pedestals below contacts to prevent short circuits, where the pedestals are made of insulating and conductive materials, and the contacts are connected to specific word lines while being insulated from surrounding layers, allowing for precise connection without penetrating the lower word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the contact is made to penetrate the conductive layer to connect to lower layers, then the connection reliability is improved, but the risk of short-circuiting with lower conductive layers increases
Solution Approach 1:
The conductive layer is segmented into multiple portions (first conductive layer portion and second conductive layer portion) with an insulating layer positioned between them. This segmentation allows the contact to penetrate through the first conductive layer portion to reach the lower conductive layer while the insulating layer prevents short-circuiting, thus resolving the contradiction between connection reliability and short-circuit risk.
Solution Approach 2:
An insulating layer is introduced as an intermediary between the first conductive layer portion and the second conductive layer portion. This insulating layer acts as a mediator that allows electrical connection through the contact while simultaneously preventing harmful short-circuits, enabling both reliable connection and short-circuit prevention.
2Ease of manufacture
If the etching conditions are made more aggressive to ensure contact penetration, then the connection formation is improved, but the precision of connecting to the specific word line deteriorates
Solution Approach 1:
The conductive layer is divided into multiple portions with an insulating layer between them, creating distinct etching zones. This segmentation allows the etching process to penetrate through the first conductive layer portion more easily while the insulating layer provides a natural stopping point that maintains precision, thus resolving the contradiction between ease of manufacture and manufacturing precision.
Solution Approach 2:
The insulating layer serves as an intermediary that facilitates the etching process by providing a clear boundary between conductive layers. This mediator enables more aggressive etching conditions to be used without compromising precision, as the insulating layer naturally limits the penetration depth and protects the second conductive layer portion.
3Object-affected harmful factors
If the contact is prevented from penetrating the lower word line, then short-circuit prevention is improved, but the risk of open defects increases
Solution Approach 1:
The conductive layer is segmented into first and second portions with an insulating layer between them. This segmentation creates a controlled penetration path where the contact can reliably connect through the first portion to the lower word line while the insulating layer prevents penetration into the second portion, thus preventing short-circuits. This resolves the contradiction by providing both reliable connection and short-circuit prevention.
Solution Approach 2:
The insulating layer acts as an intermediary that enables controlled contact penetration. It allows the contact to reach the lower word line for reliable connection while simultaneously preventing the contact from penetrating further and causing short-circuits, thus resolving the contradiction between connection reliability and short-circuit prevention.
Data Source
AI summary
A semiconductor storage device of the embodiment includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked, the stacked body including a stepped portion in which ends of the plurality of conductive layers are stepped, a pillar penetrating the stacked body, the pillar having a memory cell at a height position of each of the plurality of conductive layers, a contact disposed at the stepped portion, the contact being connected to an n-th conductive layer when counted from a lowermost conductive layer of the plurality of conductive layers, and a region in an (n−1)th conductive layer when counted from the lowermost conductive layer of the plurality of conductive layers, the region being disposed at a position below the contact, the region being insulated from the (n−1)th conductive layer surrounding a periphery.