Solid-State Devices TRIZ Cases

A display device uses a second insulating layer with gradually decreasing thickness to form storage capacitors that compensate for current differences.

Parallel light blocking bars in a wiregrid layer reflect unwanted polarized light to eliminate stress-induced phase differences and light leaks.

Segmented OLED layers with graded deuteration ratios resolve the trade-off between blue pixel efficiency and operational lifespan.

Ring-shaped transistors reduce spatial occupancy and cross-talk, enabling higher resolution.

Planarizing grinding removes height deviations from scribing processes to eliminate tilting and step issues, ensuring uniform alignment of exposed solder balls.

A first electron injection enhancing layer and a second suppressing layer balance charge carrier mobility across organic electroluminescence display device emitters.

Auxiliary lines connect to plate electrodes via via holes to form parallel resistor networks, lowering in-plane resistance and improving brightness uniformity.

External isolation films block side-emitting light to resolve manufacturing complexity while boosting top emission efficiency.

Multi-polymer adhesive layers with tailored glass transition temperatures prevent substrate detachment and crack formation under external impacts.

A front-end-of-line cavity integrates with transistor gate electrodes to define fluid inlet and outlet openings through metallization levels.

An oxide thin film transistor substrate uses an etch stopper to define the channel area and integrate data elements.

Removing molded plastic from exposed electrical contacts simplifies mold design and reduces energy loss in de-icing systems.

Mechanically interlocked host and emitter compounds enable delayed fluorescence, increasing internal quantum efficiency without covalent bonding.

Segmented second pixel electrode sub-electrodes strengthen boundary fringe fields to resolve light transmittance losses in Middle-Com PLS panels.

Positioning functional molecules in vias eliminates refresh leakage currents, reducing power consumption while maintaining high bit density.

Segmented bonding materials expose terminals without damage, resolving yield challenges.

Segmented gate electrodes and ion implantation in vertical transistors prevent floating body effect charge accumulation while maintaining channel control.

Segmenting bulk silicon and SOI regions via sealed cavities improves RF linearity while lowering manufacturing costs.

A light shielding member on the thin-film encapsulation layer blocks mixed emission from shadow portions.

Matching silicon oxynitride layers block hydrogen penetration that degrades thin film transistor characteristics while maintaining compact device volume.

Segmented linear unit cell areas with inactive regions prevent gate capacitance increase, maintaining switching speed while enhancing IE effects.

Segmented semiconductor structures bond face-to-face using intermediary contact layers, reducing alignment precision requirements and improving device yield.

Array substrate manufacturing uses metal oxidation to form dielectric layers and electrodes in fewer steps.

Diffusing elements over segmented LEDs reduce visible wall patterns to improve illumination uniformity.

Segmented gate lines control semiconductor pillars to suppress gate-induced drain leakage while maintaining high integration density.

Preparation operations minimize threshold voltage variations in semiconductor memory cells, ensuring stable switching speed and reliable data storage.

Fabricating tri-gate and dual-gate FinFETs on silicon-on-insulator wafers using selective hard mask patterning and conductive layer etching.

Segmented conductive layers with insulating pedestals prevent short circuits during contact formation, improving reliability in 3D NAND memory.

A liquid crystal array substrate uses transistors with varying charging abilities to drive sub-pixel electrodes at different deflection angles.

A recessed handle wafer structure enables deeper source drain implantation in silicon on insulator flash memory cells.

NdFxOy compounds filter visible light to improve color rendering while minimizing scattering losses.

A semiconductor spacer protection method uses a self-aligning mask to maintain shoulder margins during manufacturing.

An 8-shaped inductive coil device uses a stacked design with crossing connection segments to reduce the footprint without compromising inductance.

A component stack method integrates a surface acoustic wave filter within a transceiver housing cavity to reduce physical footprint.

Curved data lines generate a modulation electric field that deflects liquid crystal molecules, eliminating light leakage without black matrices.

Segmenting buried oxide layers optimizes charge retention for memory while eliminating floating body effects in logic devices.

An inverted image sensor die uses peripheral wire bonds to improve coplanarity and manufacturing yield in thin mobile devices.

Distance measuring devices enable continuous automatic focusing of the infrared imaging subsystem, resolving manual adjustment bottlenecks.

A flexible display panel design uses a groove in the substrate to align the stress neutral layer with metal wiring regions.

Ion implantation creates gettering sites at specific depths within a semiconductor substrate layer to capture metallic impurities.

Specific light-emitting and hole-transporting materials improve OLED efficiency by minimizing electron leakage and reducing driving voltage.

Edge bending structures isolate sealing glue from light-emitting surfaces, preventing high-temperature damage and extending display life.

A single organic compound film with carrier-trapping substances improves emission efficiency in light-emitting elements.

Viscous non-curable silicone fluid suspends inorganic phosphor particles to prevent separation and settling during storage, ensuring consistent light emission.

Deep ultraviolet photoresist patterning improves micro lens resolution and uniformity, overcoming middle ultraviolet limitations to enhance photosensitivity.

Integrating a photo-catalyst layer into the display structure adds environmental protection functions without significantly increasing device complexity.

A distributed-Bragg reflecting layer replaces absorptive metal mirrors to increase light extraction and heat dissipation efficiency.

A quantum dot LED package uses a getter and diffusion barrier to protect semiconductor layers from environmental degradation.