SOI Floating Body Memory With Bulk Logic Transistors
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Solution Overview
Problem
Existing integrated circuit memory technologies using transistors with floating bodies face challenges due to high voltage requirements on the back gate, which can degrade logic device performance and are difficult to fabricate, especially when both memory and logic devices share the same buried oxide layer.
Innovation Solution
The solution involves fabricating logic transistors in a bulk substrate while maintaining memory transistors on a silicon-on-insulator (SOI) substrate, allowing for a thinner buried oxide layer in the logic section to optimize capacitive coupling for memory and eliminate floating body effects in logic devices, thereby reducing voltage requirements and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick oxide layer is used as the buried oxide in SOI substrate, then charge retention for memory cells is improved, but the voltage required on the back gate becomes excessively high
Solution Approach 1:
The substrate is divided into two distinct sections: a first substrate section with a first buried oxide layer for memory devices and a second substrate section with a second buried oxide layer for logic devices. This segmentation allows each section to have optimized oxide thickness for its specific function, resolving the contradiction between charge retention and voltage requirements.
Solution Approach 2:
Different regions of the substrate are given different oxide layer thicknesses tailored to their specific functions. The memory section has a thicker buried oxide for charge retention, while the logic section has a thinner buried oxide for reduced voltage operation. This local differentiation resolves the contradiction by allowing each region to have optimal properties for its purpose.
2Ease of manufacture
If both memory and logic devices share the same buried oxide layer, then fabrication is simplified, but logic device performance degrades due to high voltage requirements and floating body effects
Solution Approach 1:
The substrate is segmented into memory and logic sections with different buried oxide thicknesses. This allows logic devices to operate without floating body effects and at lower voltages, improving performance while maintaining a unified fabrication approach for the overall structure.
Solution Approach 2:
The buried oxide layer thickness is locally optimized for each device type. Logic devices benefit from thinner oxide that eliminates floating body effects and reduces voltage requirements, while memory devices maintain thicker oxide for charge retention. This local quality differentiation resolves the performance degradation issue.
3Ease of operation
If a thinner buried oxide layer is used, then voltage requirements are reduced and logic device performance is improved, but charge retention for memory cells deteriorates
Solution Approach 1:
The substrate is divided into sections with different buried oxide thicknesses. The memory section maintains a thicker oxide for charge retention, while the logic section uses a thinner oxide for reduced voltage operation. This segmentation allows both requirements to be satisfied simultaneously in their respective regions.
Solution Approach 2:
Different regions have locally optimized oxide thicknesses. Memory devices operate with thicker oxide for charge retention, while logic devices operate with thinner oxide for reduced voltage requirements. This local quality approach resolves the contradiction by allowing each region to have the optimal thickness for its function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables better charge retention for memory cells while minimizing capacitive coupling issues in logic devices, enhancing overall circuit performance and allowing for optimized fabrication processes for both memory and logic components.
Implementation Method 1
maintaining a first buried oxide layer in a first section of the bulk substrate underlying the memory section and having a thickness optimized for capacitive coupling
Implementation Method 2
eliminate floating body effects in logic devices, thereby reducing voltage requirements and improving performance
Data Source
AI summary
A method and the resultant memory is described for forming an array of floating body memory cells and logic transistors on an SOI substrate. The floating bodies for the cells are formed over the buried oxide, the transistors in the logic section are formed in the bulk silicon.